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Ray ch70120ab5pr: laser-etched CAD + chip hero (factory 2.0.0 backfill) f995e28

CH70120AB5PR

COSEMITECH · Current Sensors · SOIC-8

CH70120AB5PR from COSEMITECH, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IP+ passive Positive terminal of the internal current-sense copper conduction path (fused with pin 2). Current flowing from IP+ (pins 1,2) into IP− (pins 3,4) yields a positive-slope output. Primary conductor resistance is 0.8 mΩ typical; electrically isolated from the sensor leads by 3000 VRMS.
2 IP+ passive Positive terminal of the internal current-sense copper conduction path (fused with pin 1). Carries the primary current being measured. Primary conductor resistance is 0.8 mΩ typical.
3 IP- passive Negative terminal of the internal current-sense copper conduction path (fused with pin 4). Return terminal for the primary current being measured. Electrically isolated from the low-voltage sensor leads (pins 5-8).
4 IP- passive Negative terminal of the internal current-sense copper conduction path (fused with pin 3). Return terminal for the primary current being measured.
5 GND power_in Signal ground reference for the sensor circuitry and the VIOUT output.
6 FILTER passive External filter-capacitor pin. A capacitor from FILTER to GND forms an RC low-pass with the internal 1.7 kΩ filter resistor to set the output bandwidth and adjust noise/resolution. Typical application uses ~10 nF for a bandwidth reduction, or the pin can be left with the recommended CF value from the electrical table.
7 VIOUT output Analog output voltage proportional to the sensed primary current. For the CH70120AB5 (bidirectional, ratiometric, 5 V supply), VIOUT = VCC/2 at 0 A with sensitivity 100 mV/A over ±20 A. Recommended load ≥4.7 kΩ; output can swing from VOL (≤0.2 V) to VOH (≥VCC−0.2 V).
8 VCC power_in Device power-supply input. Nominal 5 V ±0.5 V for the CH70120AB5 variant (absolute max 6 V). Supply current ICC ≈ 10 mA typical (14 mA max). Decouple with ~0.1 µF to GND close to the pin; VIOUT is ratiometric to this rail.

Key specifications

Parameter Value
Manufacturer COSEMITECH
Package SOIC-8
Category Sensor
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • CH70120AB5PR
  • CH70120AB3PR
  • CH70120BB5PR
  • CH70120CB3PR

CAD (KiCad official)

  • Symbol: CH70120AB5PR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ch70120ab5pr-etched.step / ch70120ab5pr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch70120ab5pr.step / ch70120ab5pr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: COSEMITECH datasheet (62 pp, sha256 bc54e9c5ff632dd6, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF