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CH563L

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WCH(Jiangsu Qin Heng) Microcontroller Units (MCUs/MPUs/SOCs), LQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CH563L

WCH(Jiangsu Qin Heng) · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-128(14x14)

CH563L from WCH(Jiangsu Qin Heng), in a LQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC18 power_in 1.8V core power supply for internal circuits.
2 GND power_in Common ground, 0V reference.
3 RSVD1 unconnected Reserved pin, must not be connected.
4 RSVD0 passive Reserved pin, must be connected to GND.
5 VCC18 power_in 1.8V core power supply for internal circuits.
6 RSETE passive Resistor to GND for the ETH-PHY, 12K to 18K (12K gives best performance, 18K lowest power, default 15K).
7 VCC33E power_in 3.3V power supply for the Ethernet section.
8 RSVD2 unconnected Reserved pin, must not be connected.
9 GND power_in Common ground, 0V reference.
10 RXP input Ethernet RXP signal.
11 RXN input Ethernet RXN signal.
12 VCC18E power_in 1.8V power supply for the Ethernet section.
13 VCC18E power_in 1.8V power supply for the Ethernet section.
14 TXP output Ethernet TXP signal.
15 TXN output Ethernet TXN signal.
16 GND power_in Common ground, 0V reference.
17 GND power_in Common ground, 0V reference.
18 VCC18 power_in 1.8V core power supply for internal circuits.
19 XI input Crystal oscillator input.
20 XO bidirectional Crystal oscillator inverting output.
21 VCC33U power_in 3.3V power supply for the USB section.
22 GND power_in Common ground, 0V reference.
23 RSETU passive 12K resistor to GND for the USB-PHY.
24 DN bidirectional USB bus D- (UD-) data line.
25 DP bidirectional USB bus D+ (UD+) data line.
26 VCC33U power_in 3.3V power supply for the USB section.
27 GND power_in Common ground, 0V reference.
28 VCC18 power_in 1.8V core power supply for internal circuits.
29 GND power_in Common ground, 0V reference.
30 VCC18 power_in 1.8V core power supply for internal circuits.
31 PD16 bidirectional PD16 general-purpose bidirectional I/O; alternate D16 external memory data line 16.
32 PD17 bidirectional PD17 general-purpose bidirectional I/O; alternate D17 external memory data line 17.
33 PD18 bidirectional PD18 general-purpose bidirectional I/O; alternate D18 external memory data line 18.
34 PD19 bidirectional PD19 general-purpose bidirectional I/O; alternate D19 external memory data line 19.
35 PD20 bidirectional PD20 general-purpose bidirectional I/O; alternate D20 external memory data line 20.
36 PD21 bidirectional PD21 general-purpose bidirectional I/O; alternate D21 external memory data line 21.
37 PD22 bidirectional PD22 general-purpose bidirectional I/O; alternate D22 external memory data line 22.
38 PD23 bidirectional PD23 general-purpose bidirectional I/O; alternate D23 external memory data line 23.
39 VCC33 power_in 3.3V port power supply for I/O.
40 PD24 bidirectional PD24 general-purpose bidirectional I/O; alternate D24 external memory data line 24.
41 PD25 bidirectional PD25 general-purpose bidirectional I/O; alternate D25 external memory data line 25.
42 PD26 bidirectional PD26 general-purpose bidirectional I/O; alternate D26 external memory data line 26.
43 PD27 bidirectional PD27 general-purpose bidirectional I/O; alternate D27 external memory data line 27.
44 PD28 bidirectional PD28 general-purpose bidirectional I/O; alternate D28 external memory data line 28.
45 PD29 bidirectional PD29 general-purpose bidirectional I/O; alternate D29 external memory data line 29.
46 PD30 bidirectional PD30 general-purpose bidirectional I/O; alternate D30 external memory data line 30.
47 PD31 bidirectional PD31 general-purpose bidirectional I/O; alternate D31 external memory data line 31.
48 PB0 bidirectional PB0 general-purpose I/O; alternate CTS0X (UART0 MODEM clear to send) and PWM0 pulse-width modulation output 0.
49 PB1 bidirectional PB1 general-purpose I/O; alternate DSR0X (UART0 MODEM data set ready) and CAT0 timer 0 capture input.
50 PB2 bidirectional PB2 general-purpose I/O; alternate RI0X (UART0 MODEM ring indicator) and PWM1 output 1.
51 PB3 bidirectional PB3 general-purpose I/O; alternate DCD0X (UART0 MODEM carrier detect) and CAT1 timer 1 capture input.
52 PB4 bidirectional PB4 general-purpose I/O; alternate DTR0X (UART0 MODEM data terminal ready) and PWM2 output 2.
53 PB5 bidirectional PB5 general-purpose I/O; alternate RTS0X (UART0 MODEM request to send) and CAT2 timer 2 capture input.
54 VCC18 power_in 1.8V core power supply for internal circuits.
55 GND power_in Common ground, 0V reference.
56 VCC33 power_in 3.3V port power supply for I/O.
57 PB6 bidirectional PB6 general-purpose I/O; alternate PWM3 output 3 and CAT3 timer 3 capture input.
58 PB7 bidirectional PB7 general-purpose bidirectional I/O.
59 PB16 bidirectional PB16 general-purpose I/O; alternate ADCS indicating current ADC channel 0/1 in auto-switch mode, or sampling pulse output otherwise.
60 PB17 bidirectional PB17 general-purpose I/O; alternate SCK1 SPI1 serial clock output.
61 PB18 bidirectional PB18 general-purpose I/O; alternate SDO SPI1 serial data output.
62 PB19 bidirectional PB19 general-purpose I/O; alternate SDI SPI1 data input and SDX1 SPI1 simplex-mode data I/O.
63 RST# input External reset input with internal pull-up; low level resets the device, I/O and peripherals return to defaults and the processor runs from address 0.
64 GND power_in Common ground, 0V reference.
65 AVRB power_in ADC reference negative supply, nominally same as GND but should be isolated to reduce noise.
66 AVRT power_in ADC reference positive supply, nominally same as VCC33 but should be isolated to reduce noise.
67 AIN2 input A/D conversion input channel 2.
68 AIN1 input A/D conversion input channel 1.
69 AIN0 input A/D conversion input channel 0.
70 VCC33A power_in ADC analog 3.3V supply, nominally same as VCC33 but should be isolated to reduce noise.
71 GND power_in Common ground, 0V reference.
72 VCC33 power_in 3.3V power supply for the ADC section.
73 DBG input DEBUG mode select input, active high with internal pull-down.
74 PD8 bidirectional PD8 general-purpose bidirectional I/O; alternate D8 external memory data line 8.
75 PD9 bidirectional PD9 general-purpose bidirectional I/O; alternate D9 external memory data line 9.
76 PD10 bidirectional PD10 general-purpose bidirectional I/O; alternate D10 external memory data line 10.
77 PD11 bidirectional PD11 general-purpose bidirectional I/O; alternate D11 external memory data line 11.
78 PD12 bidirectional PD12 general-purpose bidirectional I/O; alternate D12 external memory data line 12.
79 PD13 bidirectional PD13 general-purpose bidirectional I/O; alternate D13 external memory data line 13.
80 PD14 bidirectional PD14 general-purpose bidirectional I/O; alternate D14 external memory data line 14.
81 PD15 bidirectional PD15 general-purpose bidirectional I/O; alternate D15 external memory data line 15.
82 VCC18 power_in 1.8V core power supply for internal circuits.
83 VCC33 power_in 3.3V port power supply for I/O.
84 PA0 bidirectional PA0 general-purpose I/O; alternate A0 external memory address line 0.
85 PA1 bidirectional PA1 general-purpose I/O; alternate A1 external memory address line 1.
86 PA2 bidirectional PA2 general-purpose I/O; alternate A2 external memory address line 2.
87 PA3 bidirectional PA3 general-purpose I/O; alternate A3 external memory address line 3.
88 PA4 bidirectional PA4 general-purpose I/O; alternate TWP0 DEBUG breakpoint control (should be tied low) and A4 address line 4.
89 PA5 bidirectional PA5 general-purpose I/O; alternate TWP1 DEBUG breakpoint control (should be tied low) and A5 address line 5.
90 PA6 bidirectional PA6 general-purpose I/O; alternate TACK DEBUG acknowledge output and A6 address line 6.
91 PA7 bidirectional PA7 general-purpose I/O; alternate DTR0 (UART0 MODEM), TNOW0 (UART0 simplex RS485 enable), TDO and A7 address line 7.
92 VCC33 power_in 3.3V port power supply for I/O.
93 PA12 bidirectional PA12 general-purpose I/O; alternate CTS0 (UART0 MODEM clear to send) and A12 address line 12.
94 PA13 bidirectional PA13 general-purpose I/O; alternate DSR0 (UART0 MODEM), ELED# Ethernet activity LED drive, TDI and A13 address line 13.
95 PA14 bidirectional PA14 general-purpose I/O; alternate RI0 (UART0 MODEM ring indicator), TCK and A14 address line 14.
96 PA15 bidirectional PA15 general-purpose I/O; alternate DCD0 (UART0 MODEM carrier detect), TMS and A15 address line 15.
97 PA8 bidirectional 5V-tolerant PA8 general-purpose I/O; alternate RTS0 (UART0 MODEM), UID USB ID input and A8 address line 8.
98 PA9 bidirectional 5V-tolerant PA9 general-purpose I/O; alternate SLVI# slave parallel interrupt output, TRST# and A9 address line 9.
99 PA10 bidirectional 5V-tolerant PA10 general-purpose I/O; alternate SLVA slave parallel command/data select input and A10 address line 10.
100 PA11 bidirectional 5V-tolerant PA11 general-purpose I/O; alternate SLVCS# slave parallel chip select input and A11 address line 11.
101 VCC33 power_in 3.3V port power supply for I/O.
102 PA16 bidirectional 5V-tolerant PA16 general-purpose I/O; alternate CTS1 (UART1 clear to send) and A16 address line 16.
103 PA17 bidirectional 5V-tolerant PA17 general-purpose I/O; alternate RTS1 (UART1), TNOW1 (UART1 simplex RS485 enable) and A17 address line 17.
104 PA18 bidirectional 5V-tolerant PA18 general-purpose I/O; alternate ELINK# Ethernet link LED drive and A18 address line 18.
105 PA19 bidirectional 5V-tolerant PA19 general-purpose I/O; alternate VBUS USB bus power detect input and A19 address line 19.
106 PA20 bidirectional 5V-tolerant PA20 general-purpose I/O; alternate PRD# slave parallel read input / external memory read output.
107 PA21 bidirectional 5V-tolerant PA21 general-purpose I/O; alternate PWR# slave parallel write input / external memory write output.
108 VCC18 power_in 1.8V core power supply for internal circuits.
109 GND power_in Common ground, 0V reference.
110 PB8 bidirectional 5V-tolerant PB8 general-purpose I/O; alternate RXD0 UART0 receiver input.
111 PB9 bidirectional 5V-tolerant PB9 general-purpose I/O; alternate TXD0 UART0 transmitter output.
112 PB10 bidirectional 5V-tolerant PB10 general-purpose I/O; alternate RXD1 UART1 receiver input and RXTX1 UART1 simplex I/O.
113 PB11 bidirectional 5V-tolerant PB11 general-purpose I/O; alternate TXD1 UART1 transmitter output.
114 PB12 bidirectional 5V-tolerant PB12 general-purpose I/O; alternate SCS SPI0 slave chip select input.
115 PB13 bidirectional 5V-tolerant PB13 general-purpose I/O; alternate SCK0 SPI0 serial clock.
116 PB14 bidirectional 5V-tolerant PB14 general-purpose I/O; alternate MOSI SPI0 serial data (master out/slave in).
117 PB15 bidirectional 5V-tolerant PB15 general-purpose I/O; alternate MISO SPI0 serial data (master in/slave out) and SDX0 simplex data I/O.
118 PD0 bidirectional 5V-tolerant PD0 general-purpose I/O; alternate D0 external memory data line 0 and SLV_D0 slave parallel data line 0.
119 PD1 bidirectional 5V-tolerant PD1 general-purpose I/O; alternate D1 external memory data line 1 and SLV_D1 slave parallel data line 1.
120 PD2 bidirectional 5V-tolerant PD2 general-purpose I/O; alternate D2 external memory data line 2 and SLV_D2 slave parallel data line 2.
121 PD3 bidirectional 5V-tolerant PD3 general-purpose I/O; alternate D3 external memory data line 3 and SLV_D3 slave parallel data line 3.
122 VCC33 power_in 3.3V port power supply for I/O.
123 PD4 bidirectional 5V-tolerant PD4 general-purpose I/O; alternate D4 external memory data line 4 and SLV_D4 slave parallel data line 4.
124 PD5 bidirectional 5V-tolerant PD5 general-purpose I/O; alternate D5 external memory data line 5 and SLV_D5 slave parallel data line 5.
125 PD6 bidirectional 5V-tolerant PD6 general-purpose I/O; alternate D6 external memory data line 6 and SLV_D6 slave parallel data line 6.
126 PD7 bidirectional 5V-tolerant PD7 general-purpose I/O; alternate D7 external memory data line 7 and SLV_D7 slave parallel data line 7.
127 NC unconnected Reserved pin, no connect.
128 NC unconnected Reserved pin, no connect.

Key specifications

Parameter Value
Manufacturer WCH(Jiangsu Qin Heng)
Package LQFP-128(14x14)
Category Embedded Processors & Controllers
Pins 128

CAD (KiCad official)

  • Symbol: CH563L
  • Footprint: Package_QFP:LQFP-128_14x14mm_P0.4mm
  • 3D model: LQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: ch563l-etched.step / ch563l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch563l.step / ch563l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH(Jiangsu Qin Heng) datasheet (154 pp, sha256 2c3e398ea9b76f96, retrieved 2026-10-26, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF