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CH559L

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WCH(Jiangsu Qin Heng) Microcontroller Units (MCUs/MPUs/SOCs), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersch559lfactory-2.0.0extractor-text
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Symbol & Footprint

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Datasheet

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Contents

README

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CH559L

WCH(Jiangsu Qin Heng) · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-48(7x7)

CH559L from WCH(Jiangsu Qin Heng), in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.6/AIN6/MISO bidirectional Port 1 bit 6 GPIO with ADC analog input channel 6 and SPI0 MISO (master input/slave output); not 5V-tolerant.
2 P1.7/AIN7/SCK bidirectional Port 1 bit 7 GPIO with ADC analog input channel 7 and SPI0 serial clock SCK; not 5V-tolerant.
3 P5.7/RST input Port 5 bit 7 input pin, also configurable external reset input RST; the pin state is read via P5.7 in P5_IN.
4 P3.0/RXD bidirectional Port 3 bit 0 GPIO with UART0 serial data input RXD.
5 P4.5/PWM2_/A5 bidirectional Port 4 bit 5 GPIO with PWM2 mapped output and direct-address bus output A5 in xbus mode.
6 P4.4/LED3/TNOW_/TXD1_/A4 bidirectional Port 4 bit 4 GPIO with LED data3 output, mapped UART1 TNOW/TXD1 and direct-address bus output A4.
7 P3.1/TXD bidirectional Port 3 bit 1 GPIO with UART0 serial data output TXD.
8 P3.2/LED0/INT0 bidirectional Port 3 bit 2 GPIO with LED data0 output and external interrupt 0 input INT0.
9 P3.3/LED1/!A15/INT1 bidirectional Port 3 bit 3 GPIO with LED data1 output, inverted bus address A15 chip-select output (ALE disabled) and external interrupt 1 input INT1.
10 P3.4/LEDC/XCS0/T0 bidirectional Port 3 bit 4 GPIO with LED clock output, XCS0 chip-select output for 4000h-7FFFh and Timer0 external input T0.
11 P3.5/DA6/T1 bidirectional Port 3 bit 5 GPIO with direct-address bus output A6 and Timer1 external input T1.
12 P3.6/WR bidirectional Port 3 bit 6 GPIO with external bus write signal WR (active low).
13 P3.7/RD bidirectional Port 3 bit 7 GPIO with external bus read signal RD (active low).
14 P4.3/PWM1_/A3 bidirectional Port 4 bit 3 GPIO with PWM1 mapped output and direct-address bus output A3.
15 P4.2/PWM3_/CAP3_/A2 bidirectional Port 4 bit 2 GPIO with mapped PWM3/CAP3 and direct-address bus output A2.
16 P4.6/XI/SCS_ bidirectional Port 4 bit 6 GPIO, external crystal oscillator pin XI, and mapped SPI0 chip select SCS_; not 5V-tolerant.
17 P4.7/XO/SCK_ bidirectional Port 4 bit 7 GPIO, external crystal oscillator pin XO, and mapped SPI0 clock SCK_; not 5V-tolerant.
18 GND power_in Ground (VSS).
19 P4.1/A1 bidirectional Port 4 bit 1 GPIO with direct-address bus output A1.
20 P4.0/LED2/A0/RXD1_ bidirectional Port 4 bit 0 GPIO with LED data2 output, direct-address bus output A0 and mapped UART1 RXD1_.
21 P2.0/A8 bidirectional Port 2 bit 0 GPIO with bus address output A8.
22 P2.1/MOSI1/A9 bidirectional Port 2 bit 1 GPIO with SPI1 master output MOSI1 and bus address output A9.
23 P2.2/MISO1/A10 bidirectional Port 2 bit 2 GPIO with SPI1 master input MISO1 and bus address output A10.
24 P2.3/SCK1/A11 bidirectional Port 2 bit 3 GPIO with SPI1 serial clock output SCK1 and bus address output A11.
25 P2.4/PWM1/A12 bidirectional Port 2 bit 4 GPIO with PWM1 output and bus address output A12.
26 P2.5/TNOW/PWM2/A13/T2EX_/CAP2_ bidirectional Port 2 bit 5 GPIO with UART1 transmit indicator TNOW, PWM2 output, bus address A13 and mapped T2EX/CAP2.
27 P2.6/RXD1/A14 bidirectional Port 2 bit 6 GPIO with UART1 serial data input RXD1 and bus address output A14.
28 P2.7/TXD1/DA7/A15 bidirectional Port 2 bit 7 GPIO with UART1 serial data output TXD1, direct-address output A7 and bus address A15.
29 P5.5/HP/!A15/XA bidirectional Port 5 bit 5 with USB root-hub port D+ (HP), inverted A15 output when ALE output is enabled, and controllable internal pull-down resistor.
30 P5.4/HM/ALE/XB bidirectional Port 5 bit 4 with USB root-hub port D- (HM), ALE output (address latch or Fsys/12), and controllable internal pull-down resistor.
31 P5.1/DP bidirectional Port 5 bit 1 with USB data line DP (D+) and controllable internal pull-down resistor.
32 P5.0/DM bidirectional Port 5 bit 0 with USB data line DM (D-) and controllable internal pull-down resistor.
33 P0.7/AD7/UDCD bidirectional Port 0 bit 7, open-drain bidirectional by default, with xbus data/address bit AD7 and UART1 modem input UDCD.
34 P0.6/AD6/URI bidirectional Port 0 bit 6, open-drain bidirectional by default, with xbus data/address bit AD6 and UART1 modem input URI.
35 P0.5/AD5/UDSR bidirectional Port 0 bit 5, open-drain bidirectional by default, with xbus data/address bit AD5 and UART1 modem input UDSR.
36 P0.4/AD4/UCTS bidirectional Port 0 bit 4, open-drain bidirectional by default, with xbus data/address bit AD4 and UART1 modem input UCTS.
37 P0.3/AD3/TXD_ bidirectional Port 0 bit 3, open-drain bidirectional by default, with xbus data/address bit AD3 and mapped UART0 TXD_.
38 P0.2/AD2/RXD_ bidirectional Port 0 bit 2, open-drain bidirectional by default, with xbus data/address bit AD2 and mapped UART0 RXD_.
39 P0.1/AD1/URTS bidirectional Port 0 bit 1, open-drain bidirectional by default, with xbus data/address bit AD1 and UART1 modem output URTS.
40 P0.0/AD0/UDTR bidirectional Port 0 bit 0, open-drain bidirectional by default, with xbus data/address bit AD0 and UART1 modem output UDTR.
41 VIN5 power_in 5V external power input of the internal 5V->3.3V LDO; requires an external 0.1uF decoupling capacitor.
42 VDD33 power_in Internal regulator output and internal 3.3V working power input; connect VIN5 to the supply when below 3.6V, and an external 3.3uF decoupling capacitor is required above 3.6V.
43 P1.0/AIN0/T2/CAP1 bidirectional Port 1 bit 0 GPIO with ADC input channel 0, Timer2 external count input/clock output T2 and capture input CAP1; not 5V-tolerant.
44 P1.1/AIN1/T2EX/CAP2 bidirectional Port 1 bit 1 GPIO with ADC input channel 1, Timer2 reload/capture input T2EX and capture input CAP2; not 5V-tolerant.
45 P1.2/AIN2/PWM3/CAP3 bidirectional Port 1 bit 2 GPIO with ADC input channel 2 and Timer3 PWM3 output/CAP3 capture input; not 5V-tolerant.
46 P1.3/AIN3 bidirectional Port 1 bit 3 GPIO with ADC analog input channel 3; not 5V-tolerant.
47 P1.4/AIN4/SCS bidirectional Port 1 bit 4 GPIO with ADC input channel 4 and SPI0 chip select SCS; not 5V-tolerant.
48 P1.5/AIN5/MOSI bidirectional Port 1 bit 5 GPIO with ADC input channel 5 and SPI0 MOSI (master output/slave input); not 5V-tolerant.

Key specifications

Parameter Value
Manufacturer WCH(Jiangsu Qin Heng)
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating temperature TA -40 85 ℃ 91
Storage temperature TS -55 125 ℃ 91
Internal operating supply voltage VDD33 -0.4 3.6 V VCC33 connected to power, GND to ground 91
External input supply voltage VIN5 -0.4 5.6 V VIN5 connected to power, GND to ground 91
Voltage on I/O pins supporting 5V VIO5 -0.4 5.5 V 91
Internal power voltage VDD33 2.85 3.3 3.6 V TA=25℃, VIN5=5V or 3.3V, VDD33=3.3V, Fsys=12MHz 92
External input supply voltage, external capacitor on VDD33 VIN5 3.6 5 5.5 V External capacitor connected to VDD33 pin 92
External input supply voltage, VDD33 shorted to VIN5 VIN5 2.85 3.3 3.6 V VDD33 pin shorted to VIN5 pin 92
Total operating current ICC 4 8 50 mA 92
Total sleep current ISLP 0.1 0.2 mA 92
Input low voltage VIL -0.4 0.8 V 92
Input high voltage VIH 2 V max printed VDD33+0.4 92
Output low voltage VOL 0.4 V IIL = 4mA 92
Input current without pull-up resistor IIN -5 0 5 uA 92
Input current with pull-up resistor IUP 20 40 80 uA 92
Input current with pull-down resistor IDN -20 -40 -80 uA 92
Input current with pull-up resistor from low to high IUPX 200 300 500 uA 92
Power on reset threshold Vpot 2.4 2.55 2.7 V 92
External clock input frequency Fxt 4 12 20 MHz TA=25℃, VIN5=5V or 3.3V, VDD33=3.3V, Fsys=12MHz 92
Internal clock frequency Fosc 11.82 12 12.18 MHz 92
Frequency after PLL Fpll 24 288 350 MHz 92
USB sampling clock frequency, USB host Fusb4x 47.98 48 48.02 MHz USB host 92
USB sampling clock frequency, USB device Fusb4x 47.04 48 48.96 MHz USB device 92
System frequency (VDD33>=3V) Fsys 1 12 56 MHz VDD33>=3V 92
System frequency (VDD33<3V) Fsys 1 12 50 MHz VDD33<3V 92
Power on reset delay Tpor 15 17 20 mS 92
External input valid reset signal width Trst 70 100 200 nS 92
Thermal reset delay Trdl 35 60 100 uS 92
Automatically hang up time in USB host mode Tusp 2 3 4 mS USB host mode 92
Automatically hang up time in USB device mode Tusp 4 5 6 mS USB device mode 92
Time to wake up from sleep mode Twak 1 40 100 uS 92

CAD (KiCad official)

  • Symbol: CH559L
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ch559l-etched.step / ch559l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch559l.step / ch559l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH(Jiangsu Qin Heng) datasheet (93 pp, sha256 f3f1d22954ee4bb3, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF