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CH558L

Public Made by Adom

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WCH(Jiangsu Qin Heng) Microcontroller Units (MCUs/MPUs/SOCs), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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CH558L

WCH(Jiangsu Qin Heng) · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)

CH558L from WCH(Jiangsu Qin Heng), in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.6 bidirectional P1.6 GPIO with ADC input AIN6 and SPI0 MISO; not 5V tolerant (P1 pins are excluded from 5V-tolerant inputs).
2 P1.7 bidirectional P1.7 GPIO with ADC input AIN7 and SPI0 SCK; not 5V tolerant.
3 P5.7 input P5.7 / RST external reset input with built-in pull-down resistor; not 5V tolerant.
4 P3.0 bidirectional P3.0 GPIO with UART0 RXD serial data input; 5V tolerant input.
5 P4.5 bidirectional P4.5 GPIO with external bus direct-address output A5.
6 P4.4 bidirectional P4.4 GPIO with LED3 serial data output, TNOW_/TXD1_ UART1 remap and bus address A4.
7 P3.1 bidirectional P3.1 GPIO with UART0 TXD serial data output.
8 P3.2 bidirectional P3.2 GPIO with LED0 serial data output and external interrupt 0 input INT0.
9 P3.3 bidirectional P3.3 GPIO with LED1 data output, inverted bus address A15 (!A15) chip select and external interrupt 1 input INT1.
10 P3.4 bidirectional P3.4 GPIO with LEDC clock output, XCS0 chip select (bus 4000h-7FFFh) and Timer0 external input T0.
11 P3.5 bidirectional P3.5 GPIO with direct-address bus output DA6 and Timer1 external input T1.
12 P3.6 bidirectional P3.6 GPIO with external bus write strobe WR.
13 P3.7 bidirectional P3.7 GPIO with external bus read strobe RD.
14 P4.3 bidirectional P4.3 GPIO with external bus direct-address output A3.
15 P4.2 bidirectional P4.2 GPIO with PWM3_/CAP3_ (Timer3 PWM output/capture input remap) and bus address A2.
16 P4.6 bidirectional P4.6 GPIO, crystal oscillator input XI, or SPI0 SCS_ remap; not 5V tolerant.
17 P4.7 bidirectional P4.7 GPIO, crystal oscillator inverting output XO, or SPI0 SCK_ remap; not 5V tolerant.
18 GND power_in Common ground (VSS).
19 P4.1 bidirectional P4.1 GPIO with external bus direct-address output A1; selectable as GPIO interrupt source.
20 P4.0 bidirectional P4.0 GPIO with LED2 data output, bus address A0 and UART1 RXD1_ remap.
21 P2.0 bidirectional P2.0 GPIO with external bus high address output A8.
22 P2.1 bidirectional P2.1 GPIO with external bus high address output A9.
23 P2.2 bidirectional P2.2 GPIO with external bus high address output A10.
24 P2.3 bidirectional P2.3 GPIO with external bus high address output A11.
25 P2.4 bidirectional P2.4 GPIO with external bus high address output A12.
26 P2.5 bidirectional P2.5 GPIO with UART1 TNOW transmit indicator, bus address A13 and T2EX_/CAP2_ Timer2 remap.
27 P2.6 bidirectional P2.6 GPIO with UART1 RXD1 input and bus address A14.
28 P2.7 bidirectional P2.7 GPIO with UART1 TXD1 output, direct address DA7 and bus address A15.
29 P5.5 bidirectional P5.5 GPIO with inverted bus address A15 (!A15) or iRS485 XA (A/non-inverting) signal; built-in pull-down when not in iRS485 mode.
30 P5.4 bidirectional P5.4 GPIO with ALE address latch output or iRS485 XB (B/inverting) signal; built-in pull-down when not in iRS485 mode.
31 P5.1 bidirectional P5.1 GPIO / USB device D+ (DP) signal, with controllable internal pull-down.
32 P5.0 bidirectional P5.0 GPIO / USB device D- (DM) signal, with controllable internal pull-down.
33 P0.7 bidirectional P0.7 open-drain bidirectional port pin with bus data AD7 and UART1 modem input UDCD.
34 P0.6 bidirectional P0.6 open-drain bidirectional port pin with bus data AD6 and UART1 modem input URI.
35 P0.5 bidirectional P0.5 open-drain bidirectional port pin with bus data AD5 and UART1 modem input UDSR.
36 P0.4 bidirectional P0.4 open-drain bidirectional port pin with bus data AD4 and UART1 modem input UCTS.
37 P0.3 bidirectional P0.3 open-drain bidirectional port pin with bus data AD3 and UART0 TXD_ remap; selectable as GPIO interrupt source.
38 P0.2 bidirectional P0.2 open-drain bidirectional port pin with bus data AD2 and UART0 RXD_ remap.
39 P0.1 bidirectional P0.1 open-drain bidirectional port pin with bus data AD1 and UART1 modem output URTS.
40 P0.0 bidirectional P0.0 open-drain bidirectional port pin with bus data AD0 and UART1 modem output UDTR; optional internal pull-up via P0_PU.
41 VIN5 power_in 5V external supply input to the internal 5V-to-3.3V regulator; needs a 0.1uF decoupling capacitor (3.3V to 5V supply, max 5.5V typical-range).
42 VDD33 power_in Regulator output and 3.3V internal supply input; connect to VIN5 when supply is below 3.6V, otherwise add a 3.3uF decoupling capacitor (2.85V to 3.6V).
43 P1.0 bidirectional P1.0 GPIO with ADC input AIN0, Timer2 external input/clock output T2 and capture input CAP1; not 5V tolerant.
44 P1.1 bidirectional P1.1 GPIO with ADC input AIN1, Timer2 reload/capture input T2EX and capture CAP2; not 5V tolerant.
45 P1.2 bidirectional P1.2 GPIO with ADC input AIN2 and Timer3 PWM3 output/CAP3 capture input; not 5V tolerant.
46 P1.3 bidirectional P1.3 GPIO with ADC input AIN3; not 5V tolerant.
47 P1.4 bidirectional P1.4 GPIO with ADC input AIN4 and SPI0 chip select SCS (also programming chip select); not 5V tolerant.
48 P1.5 bidirectional P1.5 GPIO with ADC input AIN5 and SPI0 MOSI; not 5V tolerant.

Key specifications

Parameter Value
Manufacturer WCH(Jiangsu Qin Heng)
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating ambient temperature TA -40 85 ℃ 63
Storage temperature TS -55 125 ℃ 63
Internal supply voltage VDD33 VDD33 -0.4 3.6 V VDD33 to supply, GND to ground 63
External supply voltage VIN5 VIN5 -0.4 5.6 V VIN5 to supply, GND to ground 63
Voltage on 5V-tolerant pins VIO5 -0.4 5.6 V Max printed as VIN5+0.4; 5.6 is not printed 63
Voltage on non-5V-tolerant pins VIO3 -0.4 4 V Max printed as VDD33+0.4; 4 is not printed 64
VDD33 internal supply voltage VDD33 2.85 3.3 3.6 V TA=25℃, Fsys=12MHz 64
VIN5 supply, VDD33 with capacitor only VIN5 3.6 5 5.5 V VDD33 only external capacitor 64
VIN5 supply, VDD33 shorted to VIN5 VIN5 2.85 3.3 3.6 V VDD33 shorted to VIN5 64
Operating supply current ICC 8 50 mA Printed as 4 / 8 / 50 with only two columns attributable; 4 treated as min 64
Sleep supply current ISLP 0.1 0.2 mA Full sleep 64
Low-level input voltage VIL -0.4 0.8 V 64
Low-level output voltage VOL 0.4 V 4mA sink current 64
Input current without pull-up IIN -5 0 5 uA 64
Input current with pull-up IUP 20 40 80 uA 64
Input current with pull-down IDN -20 -40 -80 uA 64
Pull-up input current on low-to-high transition IUPX 200 300 500 uA 64
Power-on reset threshold Vpot 2.4 2.55 2.7 V 64
External crystal / XI clock frequency Fxt 4 12 20 MHz 64
Calibrated internal clock Fosc 11.82 12 12.18 MHz 64
PLL frequency Fpll 24 288 350 MHz 64
USB sampling clock Fusb4x 47.04 48 48.96 MHz USB function used 64
System clock frequency Fsys 1 12 56 MHz VDD33>=3V 64
System clock frequency Fsys 1 12 50 MHz VDD33<3V 64
Power-on reset delay Tpor 15 17 20 mS 64
External reset pulse width Trst 70 100 200 nS 64
Hot reset delay Trdl 35 60 100 uS 64
USB auto-suspend detection time Tusp 4 5 6 mS 64
Wake-up completion time after sleep Twak 1 40 100 uS 64

CAD (KiCad official)

  • Symbol: CH558L
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ch558l-etched.step / ch558l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch558l.step / ch558l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH(Jiangsu Qin Heng) datasheet (65 pp, sha256 2b45c8b5f7296514, retrieved 2026-10-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF