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CH438Q

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WCH(Jiangsu Qin Heng) RS232 ICs, LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CH438Q

WCH(Jiangsu Qin Heng) · RS232 ICs · LQFP-44(10x10)

CH438Q from WCH(Jiangsu Qin Heng), in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 WR# input Write strobe input in parallel port mode, active at low level.
2 VCC power_in Positive power terminal; supply 3.3V to 5.3V (5V typ).
3 GND power_in Common grounding end.
4 A6/ALE input Address line A6 in direct address mode; address latch enable input in multiplexed address mode, active at high level.
5 A5 input Address line input in direct address mode.
6 A4 input Address line input in direct address mode.
7 A3 input Address line input in direct address mode.
8 A2 input Address line input in direct address mode.
9 A1 input Address line input in direct address mode.
10 A0 input Address line input in direct address mode.
11 RXD4 input UART4 asynchronous serial data input with built-in weak pull-up resistor.
12 TXD4 output UART4 asynchronous serial data output.
13 TXD3 output UART3 asynchronous serial data output.
14 GND power_in Common grounding end.
15 RXD3 input UART3 asynchronous serial data input with built-in weak pull-up resistor.
16 VCC power_in Positive power terminal; supply 3.3V to 5.3V (5V typ).
17 GND power_in Common grounding end.
18 XI input Crystal oscillator input, connect external crystal and oscillation capacitor or drive external clock (0.9216MHz to 32MHz).
19 XO output Reverse-phase crystal oscillator output, connect external crystal and oscillation capacitor to ground.
20 RXD2 input UART2 asynchronous serial data input with built-in weak pull-up resistor.
21 TXD2 output UART2 asynchronous serial data output.
22 TXD1 output UART1 asynchronous serial data output.
23 RXD1 input UART1 asynchronous serial data input with built-in weak pull-up resistor.
24 TXD5 output UART5 asynchronous serial data output.
25 RXD5 input UART5 asynchronous serial data input with built-in weak pull-up resistor.
26 TXD6 output UART6 asynchronous serial data output.
27 RXD6 input UART6 asynchronous serial data input with built-in weak pull-up resistor.
28 TXD7 output UART7 asynchronous serial data output.
29 RXD7 input UART7 asynchronous serial data input with built-in weak pull-up resistor.
30 TXD0 output UART0 asynchronous serial data output.
31 RXD0 input UART0 asynchronous serial data input with built-in weak pull-up resistor.
32 INT output Open-drain interrupt request output, active at low level, external pull-up resistor may be required.
33 RST# input External manual reset input, active at low level, built-in weak pull-down resistor.
34 D7 bidirectional Bit 7 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
35 D6 bidirectional Bit 6 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
36 D5 bidirectional Bit 5 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
37 D4 bidirectional Bit 4 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
38 D3 bidirectional Bit 3 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
39 D2 bidirectional Bit 2 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
40 D1 bidirectional Bit 1 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
41 D0 bidirectional Bit 0 of the 8-bit parallel bidirectional three-state data bus; address/data multiplexed in multiplexed address mode.
42 AMOD input Address input mode selection: low level is direct address mode, high level is multiplexed address mode.
43 CS# input Chip selection control input in parallel port mode, active at low level.
44 RD# input Read strobe input in parallel port mode, active at low level.

Key specifications

Parameter Value
Manufacturer WCH(Jiangsu Qin Heng)
Package LQFP-44(10x10)
Category Interface ICs
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 3.3 5 5.3 V TA=25℃, VCC=5V 12
Supply current during working at 5V ICC 2 10 40 mA TA=25℃, VCC=5V 12
Supply current during working at 3.3V ICC3 0.5 5 20 mA 12
Supply current at 3.3V during low-power sleep ISLP3 5 50 500 uA 12
Low level input voltage VIL -0.5 0.8 V 12
High level input voltage VIH 2 V max printed as VCC+0.5 12
Low level output voltage VOL 0.5 V 4mA draw current 12
Input current of input with built-in pull-down resistor IIN 10 uA 12
Input current at input with weak pull-up resistor IUP1 2 5 170 uA 12
Input current of input with built-in weak pull-down resistor IDN1 -20 40 80 uA 12
Ambient temperature during operation (VCC=5V) TA -40 85 ℃ VCC=5V 12
Ambient temperature during operation (VCC=3.3V) TA -40 65 ℃ VCC=3.3V 12
Ambient temperature during storage TS -55 125 ℃ 12
Supply voltage VCC -0.5 6 V 12
Voltage on the input or output pins VIO -0.5 V max printed as VCC+0.5 12
XI input frequency, crystal frequency FXI 0.9216 22.1184 32 MHz max 24 at VCC=3.3V 13
Time from clear interrupt operation to cancelling interrupt TIC 2 20 100 nS 13
Width of effective strobe writing pulse WR TWW 60 nS VCC=5V 13
Width of effective strobe reading pulse RD TRW 50 nS VCC=5V 13
Interval width of strobe reading or writing pulse TWS 40 nS VCC=5V 13
Address input setup time before RD or WR TAS 5 nS VCC=5V 13
Address input maintaining time after RD or WR TAH 3 nS 13
Data input setup time before write strobe WR TIS 0 nS 13
Data input maintaining time after strobe writing WR TIH 10 nS 13
Data input hold time on write strobe WR front edge TIHX 80 nS 13
Effective strobe reading RD to effective data output TON 15 25 nS VCC=5V 13
Ineffective strobe reading RD to ineffective data output TOF 20 nS VCC=5V 13
Width of effective address latch pulse ALE TLW 6 nS VCC=5V 13
Address input setup time before address latch ALE TLS 5 nS VCC=5V 13
Address input hold time after address latch ALE TLH 3 nS 13
Multiplexed address output invalid until read strobe RD valid TLZ 0 nS 13

CAD (KiCad official)

  • Symbol: CH438Q
  • Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
  • 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: ch438q-etched.step / ch438q-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch438q.step / ch438q.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH(Jiangsu Qin Heng) datasheet (14 pp, sha256 99b5378163fd173a, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF