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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

CH341T

WCH Jiangsu Qin Heng · USB Converters · SSOP-20-208mil

CH341T from WCH Jiangsu Qin Heng, in a SSOP-20-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ACT#	output	USB device configuration status output, active low: high until the USB device is configured, low once configured; it may drive an LED through a series current-limiting resistor.
2	ROV#	tri_state	Serial receive buffer overflow indicator, active low; it should stay high in normal operation because the internal receive buffer does not normally overflow.
3	TXD	output	Asynchronous serial data output; the line idles high.
4	RXD	input	Asynchronous serial data input with internal pull-up resistor; the line idles high.
5	INT#	input	Custom interrupt request input with internal pull-up resistor, active on rising edge; a detected rising edge notifies the host computer.
6	V3	power_in	Supply pin: connect to VCC for 3.3V operation, or decouple with a 0.01uF to 0.1uF capacitor when operating at 5V.
7	UD+	bidirectional	Connects directly to the USB bus D+ data line; the USB pull-up resistor is built into the chip.
8	UD-	bidirectional	Connects directly to the USB bus D- data line.
9	XI	input	Crystal oscillator input; the CH341T requires an external 12MHz crystal with load capacitors to XI and XO.
10	XO	output	Inverted crystal oscillator output; the CH341T requires an external 12MHz crystal with load capacitor to ground.
11	GND	power_in	Common ground, connected directly to the USB bus ground; multiple GND pins are paralleled internally.
12	GND	power_in	Common ground, connected directly to the USB bus ground; multiple GND pins are paralleled internally.
13	VCC	power_in	Positive supply input with a 0.1uF decoupling capacitor; 4.0 to 5.5 V with V3 unconnected, or 3.0 to 3.6 V with V3 tied to VCC.
14	SLP#	tri_state	Sleep state output, active low.
15	SDA	bidirectional	Two-wire serial data line (open-drain output and input) with internal pull-up, used for function configuration from an external serial EEPROM.
16	SCL	output	Two-wire serial clock line (open-drain output) with internal pull-up, used for function configuration from an external serial EEPROM.
17	RDY#	output	Serial receive ready output, active low; high means the chip is not yet ready to receive data (reset, USB not configured, or receive buffer full).
18	TNOW	output	High while the chip is transmitting serial data from the serial port and low after transmission completes.
19	TEN#	input	Serial transmit enable input with internal pull-up, active low; when driven high the chip pauses serial transmission until it returns low.
20	VCC	power_in	Positive supply input with a 0.1uF decoupling capacitor; 4.0 to 5.5 V with V3 unconnected, or 3.0 to 3.6 V with V3 tied to VCC.

Key specifications

Parameter	Value
Manufacturer	WCH Jiangsu Qin Heng
Package	SSOP-20-208mil
Category	Interface
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating ambient temperature (external clock)	TA	-40		85	℃	CH341B/F/C/A/T/H chip, external clock	8
Storage ambient temperature	TS	-55		100	℃		8
Supply voltage (VCC to power, GND to ground)	VCC	-0.5		6.5	V		8
Voltage on input or output pins	VIO	-0.5			V		8
Supply voltage (V3 pin not connected to VCC)	VCC	4	5	5.5	V	V3 pin not connected to VCC pin	8
Supply voltage (V3 connected to VCC, external clock)	VCC	3	3.3	3.6	V	V3 pin connected to VCC pin, external clock	8
Operating total supply current	ICC		12	30	mA	CH341A/T/H chip, VCC=5V	8
USB suspend total supply current	ISLP		0.12	0.25	mA	VCC=5V	8
USB suspend total supply current	ISLP		0.04	0.12	mA	VCC=3.3V	8
Low-level input voltage	VIL	-0.5		0.7	V		8
High-level input voltage	VIH	2			V		8
Low-level output voltage	VOL			0.5	V	5mA 吸入电流 (5mA sink current)	8
High-level output current of SCL and SDA pins	IUPs	100	200	500	uA		8
Input current of built-in pull-up resistor input	IUP	3	120	250	uA		8
Input current of built-in pull-down resistor input	IDN	-40	-100	-250	uA		8
Power-on reset voltage threshold	VR	2.1	2.6	2.8	V		8
XI input clock signal frequency	FCLK	11.98	12	12.02	MHz		8
Power-on reset time	TPR	9	20	40	mS		8
External reset input active signal width	TRI	100			nS		8
Reset delay after external reset input	TRD		30		mS		8

CAD (KiCad official)

Symbol: CH341T
Footprint: Package_SO:SSOP-20_5.3x7.2mm_P0.65mm
3D model: SSOP-20-208mil (KiCad packages3D, STEP)
3D model files: ch341t-etched.step / ch341t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch341t.step / ch341t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: WCH Jiangsu Qin Heng datasheet (12 pp, sha256 8f76a55cf6fbe6fe, retrieved 2026-10-19, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF