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CH32X035C8T6
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WCH(Jiangsu Qin Heng) Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCH32X035C8T6
WCH(Jiangsu Qin Heng) · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
CH32X035C8T6 from WCH(Jiangsu Qin Heng), in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PA15 | bidirectional | General-purpose I/O PA15 with controllable pull-up and pull-down, and remapped USART2 TX alternates TX2_2/TX2_4. |
| 2 | PA16 | bidirectional | General-purpose I/O PA16 with controllable pull-up, and remapped USART2 RX alternates RX2_2/RX2_4. |
| 3 | PA17 | bidirectional | General-purpose I/O PA17 with controllable pull-up, and remapped USART2 CTS alternates CTS2_2/CTS2_4. |
| 4 | PA18 | bidirectional | General-purpose I/O PA18 with controllable pull-up, with TIM2 external trigger and remapped USART3 TX alternates T2ET_1/T2ET_3/TX3_2. |
| 5 | PA19 | bidirectional | General-purpose I/O PA19 with controllable pull-up, with TIM2 external trigger T2ET and remapped USART2 RX alternates RX2_1/T2ET_2. |
| 6 | PA20 | bidirectional | General-purpose I/O PA20 with controllable pull-up, with TIM2 break input T2BK and remapped USART2 TX alternates TX2_1/T2BK_2. |
| 7 | PA21 | bidirectional | General-purpose I/O PA21 with controllable pull-up, with alternate functions RST, T2C1N and remapped RTS2_2; the datasheet lists RST as a function of this pin. |
| 8 | PA22 | bidirectional | Analog-capable I/O PA22 with controllable pull-up, with TIM2 channel 2 complementary output T2C2N and CMP2 negative input C2N0. |
| 9 | PA23 | bidirectional | Analog-capable I/O PA23 with controllable pull-up, with TIM2 channel 3 complementary output T2C3N and CMP1 negative input C1N1. |
| 10 | PA0 | bidirectional | Analog-capable I/O PA0 with controllable pull-up and pull-down, with TIM2 channel 1 T2C1, USART2 CTS2, CMP1 positive input C1P1, and ADC channel A0. |
| 11 | PA1 | bidirectional | Analog-capable I/O PA1 with controllable pull-up and pull-down, with TIM2 channel 2 T2C2, USART2 RTS2, OPA1 output C1O/O1N2 and ADC channel A1. |
| 12 | PA2 | bidirectional | Analog-capable I/O PA2 with controllable pull-up and pull-down, with USART2 TX2, TIM2 channel 3 T2C3, OPA2 output O2O1 and ADC channel A2. |
| 13 | PA3 | bidirectional | Analog-capable I/O PA3 with controllable pull-up and pull-down, with TIM2 channel 4 T2C4, USART2 RX2, OPA1 output O1O0 and ADC channel A3, which is not applicable to some lots. |
| 14 | PA4 | bidirectional | Analog-capable I/O PA4 with controllable pull-up and pull-down, with SPI NSS CS, OPA2 output O2O0 and ADC channel A4. |
| 15 | PA5 | bidirectional | Analog-capable I/O PA5 with controllable pull-up and pull-down, with SPI SCK, OPA2 output O2N0 and ADC channel A5. |
| 16 | PA6 | bidirectional | Analog-capable I/O PA6 with controllable pull-up and pull-down, with SPI MISO, TIM3 channel 1 T3C1, OPA1 output O1N0 and ADC channel A6. |
| 17 | PA7 | bidirectional | Analog-capable I/O PA7 with controllable pull-up and pull-down, with SPI MOSI, TIM3 channel 2 T3C2, OPA2 output O2P0 and ADC channel A7, which is not applicable to some lots. |
| 18 | PC6 | bidirectional | General-purpose I/O PC6 with TIM1 channel 2 complementary output T1C2N and remapped SPI MISO alternate MISO_3. |
| 19 | PC7 | bidirectional | General-purpose I/O PC7 with TIM1 channel 3 complementary output T1C3N and remapped SPI MOSI alternate MOSI_3, plus PIOC_IO0_1. |
| 20 | PB0 | bidirectional | Analog-capable I/O PB0 with USART4 TX, OPA1 output O1P0 and ADC channel A8; PB0 is shorted with PA7 inside CH32X033F8P6 only. |
| 21 | PB1 | bidirectional | Analog-capable I/O PB1 with USART4 RX, OPA2 output O2N1 and ADC channel A9; PB1 and PB5 are shorted inside CH32X035G8U6 and G8R6 only. |
| 22 | PB2 | bidirectional | Analog-capable I/O PB2 with USART1 RX remap alternates RX1_3/CK4_2/CK4_5 and CMP2 output C2O. |
| 23 | PB3 | bidirectional | Analog-capable I/O PB3 with USART3 TX, CMP3 output C3O and OPA2 output O2P1. |
| 24 | PB4 | bidirectional | Analog-capable I/O PB4 with USART3 RX, TIM3 channel 1 remap T3C1_1 and OPA1 output O1P2. |
| 25 | PB5 | bidirectional | Analog-capable I/O PB5 with USART3 CK, TIM1 break input T1BK, OPA1 output O1O1 and remapped TIM3 channel 2. |
| 26 | PB6 | bidirectional | Analog-capable I/O PB6 with TIM1 channel 1 complementary output T1C1N, USART3 CTS and OPA1 output O1N1. |
| 27 | PB7 | bidirectional | Analog-capable I/O PB7 with TIM1 channel 2 complementary output T1C2N, OPA2 output O2P2 and USART3 RTS. |
| 28 | PB8 | bidirectional | Analog-capable I/O PB8 with TIM1 channel 3 complementary output T1C3N and OPA1 output O1P1. |
| 29 | PB9 | bidirectional | General-purpose I/O PB9 with TIM1 channel 1 T1C1, clock output MCO and USART4 TX remap TX4_3. |
| 30 | PB10 | bidirectional | General-purpose I/O PB10 with USART1 TX and TIM1 channel 2 T1C2. |
| 31 | PB11 | bidirectional | General-purpose I/O PB11 with TIM1 channel 3 T1C3 and USART1 RX. |
| 32 | PC16 | bidirectional | Analog-capable I/O PC16 with USB D- (UDM), TIM1 channel 4 T1C4, USART4 TX/RX and I2C, and it requires an external pull-up when I2C is used; PC16 and PC11 are shorted inside the package. |
| 33 | PC17 | bidirectional | Analog-capable I/O PC17 with USB D+ (UDP), USART1 RTS and TIM1 external trigger; it is the BOOT detection pin, sampled high at power-up, and PC17 and PC10 are shorted inside the package. |
| 34 | PC18 | bidirectional | General-purpose I/O PC18 with SWDIO (DIO) and PIOC_IO0 as the default function, plus USART3 TX remap TX3_1 and TIM1 external trigger alternates. |
| 35 | PB12 | bidirectional | General-purpose I/O PB12 with TIM1 channel 4 T1C4_2, TIM2 complementary channel 2 T2C2N_5 and USART1 CK remap CK1_3. |
| 36 | PB13 | bidirectional | General-purpose I/O PB13 with USART4 TX remap TX4_4. |
| 37 | PC19 | bidirectional | Analog-capable I/O PC19 with SWCLK (DCK) and PIOC_IO1 as functions, plus TIM2 channel 1 T2C1_5, CMP1 output C1P0 and I2C alternates. |
| 38 | PC14 | bidirectional | Analog-capable I/O PC14 with CC1 (Type-C configuration channel 1), TIM1 channel 3 remap T1C3_4 and TIM2 channel 2 remap T2C2_6. |
| 39 | PC15 | bidirectional | Analog-capable I/O PC15 with CC2 (Type-C configuration channel 2), TIM2 channel 3 remap T2C3_6 and TIM1 external trigger T1ET_4. |
| 40 | PA8 | bidirectional | General-purpose I/O PA8 with USART4 RTS as default function, plus remapped USART1 RTS and SPI MISO alternates. |
| 41 | PA9 | bidirectional | General-purpose I/O PA9 with remapped SPI MOSI_1, USART4 RX_1, USART1 CTS_2 and TIM2 break input T2BK_1/T2BK_3. |
| 42 | PA10 | bidirectional | General-purpose I/O PA10 with I2C SCL (flagged for some lots) and remapped USART1 TX_1, SPI MOSI_2 and USART4 RX_3. |
| 43 | PA11 | bidirectional | Analog-capable I/O PA11 with I2C SDA (flagged for some lots), CMP2 positive input C2P1, USART1 RX_1 and SPI SCK_2. |
| 44 | PA12 | bidirectional | Analog-capable I/O PA12 with CMP2 positive input C2P0, SPI CS_2 and TIM2 channel 2 and channel 1N remaps. |
| 45 | PA13 | bidirectional | Analog-capable I/O PA13 with CMP3 positive input C3P0, I2C SCL_1, USART4 RTS_3, USART1 CTS_3 and TIM2 remap alternates. |
| 46 | PA14 | bidirectional | Analog-capable I/O PA14 with CMP3 positive input C3P1, I2C SDA_1, USART1 RTS_3, USART4 CTS_3 and TIM2 channel 3N remaps. |
| 47 | GND | power_in | Ground reference pin for the device; the voltage difference between GND pins is limited to 20 mV. |
| 48 | VDD | power_in | Main supply pin for I/O and the internal regulator, with an operating range of 2.0 to 5.5V and a minimum of 2.5V when ADC or PD is used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WCH(Jiangsu Qin Heng) |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient temperature, operating | TA | -40 | 85 | ℃ | 23 | ||
| Ambient temperature, storage | TS | -40 | 125 | ℃ | 23 | ||
| Supply voltage on VDD pin | VDD | -0.3 | 6 | V | 23 | ||
| I/O pin voltage | VIN | -0.3 | V | max VDD+0.3 V | 23 | ||
| Voltage difference between VDD pins | /ΔVDD_x/ | 20 | mV | 23 | |||
| Voltage difference between GND pins | /ΔGND_x/ | 20 | mV | 23 | |||
| Total current through all VDD pins | IVDD | 150 | mA | 23 | |||
| Total current through all GND pins | IGND | 200 | mA | 23 | |||
| Sink current per I/O pin | IIO | 40 | mA | any I/O pin sink current | 23 | ||
| Source current per I/O pin | IIO | 30 | mA | any I/O pin source current | 23 | ||
| Internal system bus / CPU clock frequency | FHCLK or FSYS | 48 | MHz | 23 | |||
| Supply voltage VDD | VDD | 2 | 5.5 | V | USB and PD functions not used | 23 | |
| Supply voltage VDD | VDD | 3 | 5.3 | V | USB or PD functions used | 23 | |
| Supply voltage VDD | VDD | 2.5 | 5.5 | V | ADC function used | 24 | |
| VDD rise rate | tVDD | 0.1 | us/V | VDD rising | 24 | ||
| VDD fall rate | tVDD | 10 | us/V | VDD falling | 24 | ||
| PVD threshold, rising edge | VPVD | 2.12 | V | PLS[1:0] = 00 上升沿 | 24 | ||
| PVD threshold, falling edge | VPVD | 2.1 | V | PLS[1:0] = 00 下降沿 | 24 | ||
| PVD threshold, rising edge | VPVD | 2.32 | V | PLS[1:0] = 01 上升沿 | 24 | ||
| PVD threshold, falling edge | VPVD | 2.3 | V | PLS[1:0] = 01 下降沿 | 24 | ||
| PVD threshold, rising edge | VPVD | 3.02 | V | PLS[1:0] = 10 上升沿 | 24 | ||
| PVD threshold, falling edge | VPVD | 3 | V | PLS[1:0] = 10 下降沿 | 24 | ||
| PVD threshold, rising edge | VPVD | 4.02 | V | PLS[1:0] = 11 上升沿 | 24 | ||
| PVD threshold, falling edge | VPVD | 4 | V | PLS[1:0] = 11 下降沿 | 24 | ||
| PVD hysteresis | VPVDhyst | 20 | mV | 24 | |||
| Power-on/power-down reset threshold, rising edge | VPOR/PDR | 1.8 | V | 上升沿 | 24 | ||
| Power-on/power-down reset threshold, falling edge | VPOR/PDR | 1.78 | V | 下降沿 | 24 | ||
| PDR hysteresis | VPDRhyst | 20 | mV | 24 | |||
| Reset delay, power-on reset | tRSTTEMPO | 4 | 17 | 24 | ms | 上电复位 | 24 |
| Reset delay, other resets | tRSTTEMPO | 6 | 9 | 20 | us | 其他复位 | 24 |
| Internal reference voltage | VREFINT | 1.16 | 1.2 | 1.24 | V | TA = -40℃～85℃ | 24 |
CAD (KiCad official)
- Symbol:
CH32X035C8T6 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
ch32x035c8t6-etched.step/ch32x035c8t6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ch32x035c8t6.step/ch32x035c8t6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WCH(Jiangsu Qin Heng) datasheet (41 pp, sha256
147f0d22d0738729, retrieved 2026-10-27, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).