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CH32V303RCT6

Public Made by Adom

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WCH Others, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CH32V303RCT6

WCH · Others · LQFP-64(10x10)

CH32V303RCT6 from WCH, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply input (1.8 V to 3.6 V) that powers the RTC, external LSE and backup registers when VDD is off; it must not exceed VDD.
2 PC13/TAMPER-RTC bidirectional General-purpose I/O with TAMPER-RTC function; when powered from VDD it is limited to 2 MHz GPIO output with 30 pF maximum load and cannot drive LEDs, and when powered from VBAT it can only be used as TAMPER, RTC alarm or second output.
3 PC14/OSC32_IN bidirectional Backup-domain I/O used as LSE oscillator input (OSC32_IN); from VDD it is limited to 2 MHz GPIO output with 30 pF load, and from VBAT it can only be used for LSE.
4 PC15/OSC32_OUT bidirectional Backup-domain I/O used as LSE oscillator output (OSC32_OUT); from VDD it is limited to 2 MHz GPIO output with 30 pF load, and from VBAT it can only be used for LSE.
5 OSC_IN/PD0 input HSE crystal/external clock input (3 to 25 MHz); this pin defaults to OSC_IN after reset on the LQFP64M package and can be reassigned to PD0 by software.
6 OSC_OUT/PD1 output HSE crystal oscillator output; this pin defaults to OSC_OUT after reset on the LQFP64M package and can be reassigned to PD1 by software.
7 NRST input Active-low external reset input with internal pull-up of about 30 to 50 kOhm and 100 ns minimum filtered pulse width.
8 PC0 bidirectional Analog-capable I/O with ADC_IN10 input; alternate functions include TIM9_CH1N, UART6_TX and ETH_RGMII_RXC.
9 PC1 bidirectional Analog-capable I/O with ADC_IN11 input; alternate functions include TIM9_CH2N, UART6_RX, ETH_MII_MDC and ETH_RMII_MDC.
10 PC2 bidirectional Analog-capable I/O with ADC_IN12 input; alternate functions include TIM9_CH3N, UART7_TX and OPA3_CH1N.
11 PC3 bidirectional Analog-capable I/O with ADC_IN13 input; alternate functions include TIM10_CH3, UART7_RX and OPA4_CH1N.
12 VSSA power_in Analog ground for the ADC, temperature sensor, DAC, OPA, high-frequency RC oscillator and PLL analog parts.
13 VDDA power_in Analog supply (2.4 V to 3.6 V) for the ADC, DAC, OPA, RC oscillator and PLL; it must be the same voltage as VIO, and must be at least 2.4 V when the ADC is used.
14 PA0-WKUP bidirectional I/O with ADC_IN0 input and WKUP wake-up function (rising edge wakes the device from standby); alternates include USART2_CTS, TIM2_CH1/TIM2_ETR, TIM5_CH1, TIM8_ETR and OPA4_OUT0.
15 PA1 bidirectional I/O with ADC_IN1 input; alternate functions include USART2_RTS, TIM5_CH2, TIM2_CH2 and OPA3_OUT0.
16 PA2 bidirectional I/O with ADC_IN2 input; alternate functions include USART2_TX, TIM5_CH3, TIM2_CH3, TIM9_CH1 and OPA2_OUT0.
17 PA3 bidirectional I/O with ADC_IN3 input; alternate functions include USART2_RX, TIM5_CH4, TIM2_CH4, TIM9_CH2 and OPA1_OUT0.
18 VSS_4 power_in Digital ground pin; differences between ground pins must not exceed 50 mV.
19 VDD_4 power_in Main digital supply (2.4 V to 3.6 V) for part of the I/O pins and the internal regulator; differences between supply pins must not exceed 50 mV.
20 PA4 bidirectional I/O with ADC_IN4 and DAC1_OUT analog functions; alternate functions include SPI1_NSS, USART2_CK, TIM9_CH3 and DVP_HSYNC.
21 PA5 bidirectional I/O with ADC_IN5 and DAC2_OUT analog functions; alternate functions include SPI1_SCK, OPA2_CH1N, DVP_VSYNC and USART1_CTS_2.
22 PA6 bidirectional I/O with ADC_IN6 input; alternate functions include SPI1_MISO, TIM8_BKIN, TIM3_CH1, OPA1_CH1N and DVP_PCLK.
23 PA7 bidirectional I/O with ADC_IN7 input; alternate functions include SPI1_MOSI, TIM8_CH1N, TIM3_CH2, OPA2_CH1P and TIM1_CH1N_1.
24 PC4 bidirectional I/O with ADC_IN14 input; alternate functions include TIM9_CH4, UART8_TX, OPA4_CH1P and USART1_CTS_3.
25 PC5 bidirectional I/O with ADC_IN15 input; alternate functions include TIM9_BKIN, UART8_RX, OPA3_CH1P and USART1_RTS_3.
26 PB0 bidirectional I/O with ADC_IN8 input; alternate functions include TIM3_CH3, TIM8_CH2N, OPA1_CH1P, TIM1_CH2N_1 and UART4_TX_1.
27 PB1 bidirectional I/O with ADC_IN9 input; alternate functions include TIM3_CH4, TIM8_CH3N, OPA4_CH0N, TIM1_CH3N_1 and UART4_RX_1.
28 PB2/BOOT1 bidirectional I/O that also serves as BOOT1 boot-mode select; for low-power states the datasheet recommends configuring it as input with pull-down to avoid extra current.
29 PB10 bidirectional 5 V tolerant I/O (FT); alternate functions include I2C2_SCL, USART3_TX, OPA2_CH0N, TIM2_CH3_2 and TIM10_BKIN_1.
30 PB11 bidirectional 5 V tolerant I/O (FT); alternate functions include I2C2_SDA, USART3_RX, OPA1_CH0N, TIM2_CH4_2 and TIM10_ETR_1.
31 VSS_1 power_in Digital ground pin; differences between ground pins must not exceed 50 mV.
32 VIO_1 power_in I/O supply (2.4 V to 3.6 V) that sets the high output level of most I/O pins; it must not be higher than VDD in normal operation.
33 PB12 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, OPA4_CH0P and CAN2_RX.
34 PB13 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, OPA3_CH0P and CAN2_TX.
35 PB14 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI2_MISO, TIM1_CH2N, USART3_RTS, OPA2_CH0P and SDIO_D0 (SDIO_D0 default mapping changes per note 7 under certain batch and ETH/SDIO conditions).
36 PB15 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI2_MOSI, I2S2_SD, TIM1_CH3N, OPA1_CH0P, SDIO_D1 and USART1_TX_2.
37 PC6 bidirectional 5 V tolerant I/O (FT); alternate functions include I2S2_MCK, TIM8_CH1, SDIO_D6, ETH_RXP and TIM3_CH1_3.
38 PC7 bidirectional 5 V tolerant I/O (FT); alternate functions include I2S3_MCK, TIM8_CH2, SDIO_D7, ETH_RXN and TIM3_CH2_3.
39 PC8 bidirectional 5 V tolerant I/O (FT); alternate functions include TIM8_CH3, SDIO_D0, ETH_TXP, DVP_D2 and TIM3_CH3_3.
40 PC9 bidirectional 5 V tolerant I/O (FT); alternate functions include TIM8_CH4, SDIO_D1, ETH_TXN, DVP_D3 and TIM3_CH4_3.
41 PA8 bidirectional 5 V tolerant I/O (FT); alternate functions include USART1_CK, TIM1_CH1, MCO clock output, I2S3_MCK and USART1_RX_2.
42 PA9 bidirectional 5 V tolerant I/O (FT); alternate functions include USART1_TX, TIM1_CH2, OTG_FS_VBUS, I2S3_SD and DVP_D0.
43 PA10 bidirectional 5 V tolerant I/O (FT); alternate functions include USART1_RX, TIM1_CH3, OTG_FS_ID, DVP_D1 and USART1_CK_2.
44 PA11 bidirectional 5 V tolerant I/O (FT) and USB pin (OTG_FS_DM, ESD 3 kV HBM); alternate functions include USART1_CTS, CAN1_RX and TIM1_CH4.
45 PA12 bidirectional 5 V tolerant I/O (FT) and USB pin (OTG_FS_DP, ESD 3 kV HBM); alternate functions include USART1_RTS, CAN1_TX, TIM1_ETR and TIM10_CH1N.
46 PA13/SWDIO bidirectional 5 V tolerant I/O (FT) whose default function after reset is the SWDIO serial-wire debug data line; alternate functions include TIM10_CH2N, TIM8_CH1N_1 and USART3_TX_2.
47 VSS_2 power_in Digital ground pin; differences between ground pins must not exceed 50 mV.
48 VDD_2 power_in Main digital supply (2.4 V to 3.6 V) for part of the I/O pins and the internal regulator; it must be within 50 mV of the other VDD pins.
49 PA14/SWCLK bidirectional 5 V tolerant I/O (FT) whose default function after reset is the SWCLK serial-wire debug clock; alternate functions include TIM10_CH3N, TIM8_CH2N_1, UART8_TX_1 and USART3_RX_2.
50 PA15 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI3_NSS, SPI3_MOSI, I2S3_WS, TIM2_CH1_1/TIM2_ETR_1, SPI1_NSS_1 and UART8_RX_1.
51 PC10 bidirectional 5 V tolerant I/O (FT); alternate functions include UART4_TX, SDIO_D2, TIM10_ETR, DVP_D8, USART3_TX_1 and SPI3_SCK_1.
52 PC11 bidirectional 5 V tolerant I/O (FT); alternate functions include UART4_RX, SDIO_D3, TIM10_CH4, DVP_D4, USART3_RX_1 and SPI3_MISO_1.
53 PC12 bidirectional 5 V tolerant I/O (FT); alternate functions include UART5_TX, SDIO_CK, TIM10_BKIN, DVP_D9, USART3_CK_1 and SPI3_MOSI_1.
54 PD2 bidirectional 5 V tolerant I/O (FT); alternate functions include TIM3_ETR, UART5_RX, SDIO_CMD and DVP_D11, and FSMC_NADV mapping follows note 9 under certain batch and USBHS/FSMC conditions.
55 PB3 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI3_SCK, I2S3_CK, TIM2_CH2_1, SPI1_SCK_1 and TIM10_CH1_1, and DVP_D5 mapping follows note 8.
56 PB4 bidirectional 5 V tolerant I/O (FT); alternate functions include SPI3_MISO, TIM3_CH1_2, SPI1_MISO_1, UART5_TX_1 and TIM10_CH2_1.
57 PB5 bidirectional 5 V tolerant I/O (FT); alternate functions include I2C1_SMBA, SPI3_MOSI, I2S3_SD, TIM3_CH2_2, SPI1_MOSI_1, CAN2_RX_1 and UART5_RX_1.
58 PB6 bidirectional 5 V tolerant I/O (FT) and USB pin (USBHS_DM); alternate functions include I2C1_SCL, TIM4_CH1, USART1_TX_1, CAN2_TX_1 and TIM8_CH1_1, and DVP_D5 mapping follows note 8.
59 PB7 bidirectional 5 V tolerant I/O (FT) and USB pin (USBHS_DP); alternate functions include I2C1_SDA, TIM4_CH2, USART1_RX_1 and TIM8_CH2_1, and FSMC_NADV mapping follows note 9.
60 BOOT0 input Boot-mode select input (BOOT0) sampled at startup; together with BOOT1 it selects boot from main flash, system memory or internal SRAM.
61 PB8 bidirectional I/O with 5 V tolerance (FT); alternate functions include TIM4_CH3, SDIO_D4, TIM10_CH1, DVP_D6, ETH_MII_TXD3, I2C1_SCL_1 and CAN1_RX_2.
62 PB9 bidirectional I/O with 5 V tolerance (FT); alternate functions include TIM4_CH4, SDIO_D5, TIM10_CH2, DVP_D7, I2C1_SDA_1, CAN1_TX_2 and UART6_RX_1.
63 VSS_3 power_in Digital ground pin; differences between ground pins must not exceed 50 mV.
64 VIO_3 power_in I/O supply (2.4 V to 3.6 V) that sets the high output level of the I/O pins it feeds; it must not be higher than VDD in normal operation.

Key specifications

Parameter Value
Manufacturer WCH
Package LQFP-64(10x10)
Category Others
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating ambient temperature TA -40 85 ℃ 除 CH32V303RCT7 (applies to CH32V303RCT6) 48
Storage ambient temperature TS -40 125 ℃ 48
External main supply voltage (including VDDA and VDD) VDD-VSS -0.3 4 V 48
IO supply voltage VIO-VSS -0.3 4 V 48

CAD (KiCad official)

  • Symbol: CH32V303RCT6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ch32v303rct6-etched.step / ch32v303rct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch32v303rct6.step / ch32v303rct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH datasheet (84 pp, sha256 e2cb4e6f003250be, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF