component
CH32V303CBT6
Public Made by Adomby adom
WCH Jiangsu Qin Heng Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 9d ago |
| viewers | 9d ago |
| ch32v303cbt6-etched.glb | 9d ago |
| ch32v303cbt6-etched.step | 9d ago |
| ch32v303cbt6-hero.glb | 9d ago |
| ch32v303cbt6-hero.overlay.json | 9d ago |
| ch32v303cbt6.glb | 9d ago |
| ch32v303cbt6.kicad_mod | 9d ago |
| ch32v303cbt6.kicad_sym | 9d ago |
| ch32v303cbt6.lbr | 9d ago |
| ch32v303cbt6.step | 9d ago |
| package.json | 9d ago |
| page.json | 9d ago |
| README.md | 9d ago |
CH32V303CBT6
WCH Jiangsu Qin Heng · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)
CH32V303CBT6 from WCH Jiangsu Qin Heng, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup supply input, 1.8-3.6 V, powers the RTC, LSE and backup registers when VDD is removed; keep the battery connection short. |
| 2 | PC13 | bidirectional | GPIO, TAMPER-RTC input and RTC alarm/second output; when powered from VDD it is limited to 2 MHz with 30 pF load and cannot source LED current. |
| 3 | PC14/OSC32_IN | bidirectional | GPIO or LSE oscillator input; as a GPIO output it is limited to 2 MHz and 30 pF, and it is LSE-only when powered from VBAT. |
| 4 | PC15/OSC32_OUT | bidirectional | GPIO or LSE oscillator output; same limits as PC14 (2 MHz, 30 pF as GPIO output, LSE-only when powered from VBAT). |
| 5 | OSC_IN/PD0 | input | HSE oscillator input for a 3-25 MHz crystal or external clock; PD0 is the alternate function on this pin. |
| 6 | OSC_OUT/PD1 | output | HSE oscillator output for a 3-25 MHz crystal; PD1 is the alternate function on this pin. |
| 7 | NRST | input | Active-low external reset input with an internal pull-up of 30-50 kΩ. |
| 8 | VSSA | power_in | Analog ground reference for ADC, DAC, OPA, RC oscillator and PLL. |
| 9 | VDDA | power_in | Analog supply, 2.4-3.6 V; must equal VIO, and must be at least 2.4 V when the ADC is used. |
| 10 | PA0/WKUP/ADC0 | bidirectional | GPIO with WKUP wake-up input, ADC_IN0 analog input, USART2_CTS, TIM2_CH1/ETR and OPA4_OUT0. |
| 11 | PA1/ADC1 | bidirectional | GPIO with ADC_IN1 analog input, USART2_RTS, TIM2_CH2 and OPA3_OUT0. |
| 12 | PA2/ADC2 | bidirectional | GPIO with ADC_IN2 analog input, USART2_TX, TIM2_CH3 and OPA2_OUT0. |
| 13 | PA3/ADC3 | bidirectional | GPIO with ADC_IN3 analog input, USART2_RX, TIM2_CH4 and OPA1_OUT0. |
| 14 | PA4/ADC4/DAC0 | bidirectional | GPIO with ADC_IN4 analog input, DAC1_OUT, SPI1_NSS and USART2_CK. |
| 15 | PA5/ADC5/DAC1 | bidirectional | GPIO with ADC_IN5 analog input, DAC2_OUT, SPI1_SCK and OPA2_CH1N. |
| 16 | PA6/ADC6 | bidirectional | GPIO with ADC_IN6 analog input, SPI1_MISO, TIM3_CH1 and OPA1_CH1N. |
| 17 | PA7/ADC7 | bidirectional | GPIO with ADC_IN7 analog input, SPI1_MOSI, TIM3_CH2 and OPA2_CH1P. |
| 18 | PB0/ADC8 | bidirectional | GPIO with ADC_IN8 analog input, TIM3_CH3 and OPA1_CH1P. |
| 19 | PB1/ADC9 | bidirectional | GPIO with ADC_IN9 analog input, TIM3_CH4 and OPA4_CH0N. |
| 20 | PB2/BOOT1 | bidirectional | 5 V tolerant GPIO that is sampled as BOOT1 for boot mode selection at startup; also OPA3_CH0N. |
| 21 | PB10 | bidirectional | 5 V tolerant GPIO with I2C2_SCL, USART3_TX and OPA2_CH0N. |
| 22 | PB11 | bidirectional | 5 V tolerant GPIO with I2C2_SDA, USART3_RX and OPA1_CH0N. |
| 23 | VSS_1 | power_in | Digital ground. |
| 24 | VDD_IO_1 | power_in | I/O supply for this GPIO group, 2.4-3.6 V; must not be higher than VDD during normal operation. |
| 25 | PB12 | bidirectional | 5 V tolerant GPIO with SPI2_NSS, I2C2_SMBA, USART3_CK, TIM1_BKIN and OPA4_CH0P. |
| 26 | PB13 | bidirectional | 5 V tolerant GPIO with SPI2_SCK, USART3_CTS, TIM1_CH1N and OPA3_CH0P. |
| 27 | PB14 | bidirectional | 5 V tolerant GPIO with SPI2_MISO, TIM1_CH2N, USART3_RTS and OPA2_CH0P. |
| 28 | PB15 | bidirectional | 5 V tolerant GPIO with SPI2_MOSI, TIM1_CH3N and OPA1_CH0P. |
| 29 | PA8 | bidirectional | 5 V tolerant GPIO with USART1_CK, TIM1_CH1 and MCO clock output. |
| 30 | PA9 | bidirectional | 5 V tolerant GPIO with USART1_TX, TIM1_CH2 and OTG_FS_VBUS. |
| 31 | PA10 | bidirectional | 5 V tolerant GPIO with USART1_RX, TIM1_CH3 and OTG_FS_ID. |
| 32 | PA11/USB1DM | bidirectional | 5 V tolerant GPIO with USART1_CTS, CAN1_RX, TIM1_CH4 and OTG_FS_DM (USB full-speed D-). |
| 33 | PA12/USB1DP | bidirectional | 5 V tolerant GPIO with USART1_RTS, CAN1_TX, TIM1_ETR and OTG_FS_DP (USB full-speed D+). |
| 34 | PA13/SWDIO | bidirectional | 5 V tolerant; serial-wire debug data I/O (SWDIO) at reset, otherwise GPIO PA13. |
| 35 | VSS_2 | power_in | Digital ground. |
| 36 | VDD_2 | power_in | Digital supply, 2.4-3.6 V (3.0-3.6 V when USB is used). |
| 37 | PA14/SWCLK | bidirectional | 5 V tolerant; serial-wire debug clock (SWCLK) at reset, otherwise GPIO PA14. |
| 38 | PA15 | bidirectional | 5 V tolerant GPIO with SPI3_NSS, SPI3_MOSI and SPI1_NSS remap. |
| 39 | PB3 | bidirectional | 5 V tolerant GPIO with SPI3_SCK, TIM2_CH2 remap and SPI1_SCK remap. |
| 40 | PB4 | bidirectional | 5 V tolerant GPIO with SPI3_MISO, TIM3_CH1 remap and SPI1_MISO remap. |
| 41 | PB5 | bidirectional | 5 V tolerant GPIO with I2C1_SMBA, SPI3_MOSI, TIM3_CH2 remap and SPI1_MOSI remap. |
| 42 | PB6 | bidirectional | 5 V tolerant GPIO with I2C1_SCL, TIM4_CH1 and USART1_TX remap. |
| 43 | PB7 | bidirectional | 5 V tolerant GPIO with I2C1_SDA, TIM4_CH2 and USART1_RX remap. |
| 44 | BOOT0 | input | Boot mode select input sampled at startup together with BOOT1. |
| 45 | PB8 | bidirectional | 5 V tolerant GPIO with TIM4_CH3, I2C1_SCL remap and CAN1_RX remap. |
| 46 | PB9 | bidirectional | 5 V tolerant GPIO with TIM4_CH4, I2C1_SDA remap and CAN1_TX remap. |
| 47 | VSS_3 | power_in | Digital ground. |
| 48 | VDD_IO_3 | power_in | I/O supply for this GPIO group, 2.4-3.6 V; must not be higher than VDD during normal operation. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WCH Jiangsu Qin Heng |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage on FT (5V-tolerant) pins | VIN | 5.5 | V | FT (5V-tolerant) pins; min printed as VSS-0.3, not a numeric value | 51 | ||
| External main supply voltage (includes VDDA and VDD) | VDD-VSS | -0.3 | 4 | V | 51 | ||
| I/O supply voltage | VIO-VSS | -0.3 | 4 | V | 51 | ||
| Ambient temperature under bias | TA | -40 | 85 | ℃ | Chip with model last digit 6 | 51 | |
| Storage ambient temperature | TS | -40 | 125 | ℃ | 51 |
CAD (KiCad official)
- Symbol:
CH32V303CBT6 - Footprint:
Package_QFP:LQFP-48_7x7mm_P0.5mm - 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files:
ch32v303cbt6-etched.step/ch32v303cbt6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ch32v303cbt6.step/ch32v303cbt6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WCH Jiangsu Qin Heng datasheet (87 pp, sha256
5f87f9f397529ca8, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).