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CH32V103C8T6

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WCH Jiangsu Qin Heng Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CH32V103C8T6

WCH Jiangsu Qin Heng · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

CH32V103C8T6 from WCH Jiangsu Qin Heng, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup-domain supply, 1.8 V to 5.5 V and must not exceed VDD; it powers the RTC, the external 32 kHz oscillator and the backup registers when VDD is removed.
2 PC13-TAMPER-RTC bidirectional General-purpose I/O when the backup domain is powered from VDD; acts as TAMPER input, RTC alarm or second output when powered from VBAT, and in VDD mode as output it is limited to 2 MHz with max 30 pF load.
3 PC14-OSC32_IN bidirectional GPIO or LSE (32.768 kHz oscillator) input when the backup domain is powered from VDD; restricted to the LSE function only when powered from VBAT.
4 PC15-OSC32_OUT bidirectional GPIO or LSE (32.768 kHz oscillator) output when the backup domain is powered from VDD; restricted to the LSE function only when powered from VBAT.
5 OSC_IN input External high-speed oscillator input (4-16 MHz crystal or resonator) that is the default function after reset; can be reconfigured as PD0.
6 OSC_OUT output External high-speed oscillator output (4-16 MHz crystal or resonator) that is the default function after reset; can be reconfigured as PD1.
7 NRST bidirectional External reset pin; input low level max 0.8 V and input high level min 0.65·VDD, with 330 mV Schmitt hysteresis.
8 VSSA power_in Analog ground for the ADC, temperature sensor and PLL analog section; must be connected to VSS.
9 VDDA power_in Analog supply for the ADC, temperature sensor and PLL, 2.7 V to 5.5 V without ADC (must equal VDD) or 3.0 V to 5.5 V when the ADC is used; must be connected to VDD.
10 PA0-WKUP bidirectional Analog-capable GPIO that also serves as WKUP wake-up input (rising edge) with ADC_IN0, TIM2_CH1/TIM2_ETR and USART2_CTS.
11 PA1 bidirectional Analog-capable GPIO with ADC_IN1, TIM2_CH2 and USART2_RTS alternate functions.
12 PA2 bidirectional Analog-capable GPIO with ADC_IN2, TIM2_CH3 and USART2_TX alternate functions.
13 PA3 bidirectional Analog-capable GPIO with ADC_IN3, TIM2_CH4 and USART2_RX alternate functions.
14 PA4 bidirectional Analog-capable GPIO with ADC_IN4, SPI1_NSS and USART2_CK alternate functions.
15 PA5 bidirectional Analog-capable GPIO with ADC_IN5 and SPI1_SCK alternate functions.
16 PA6 bidirectional Analog-capable GPIO with ADC_IN6, SPI1_MISO and TIM3_CH1 alternate functions; TIM1_BKIN_1 is available by remap.
17 PA7 bidirectional Analog-capable GPIO with ADC_IN7, SPI1_MOSI and TIM3_CH2 alternate functions; TIM1_CH1N_1 is available by remap.
18 PB0 bidirectional Analog-capable GPIO with ADC_IN8 and TIM3_CH3 alternate functions; TIM1_CH2N_1 is available by remap.
19 PB1 bidirectional Analog-capable GPIO with ADC_IN9 and TIM3_CH4 alternate functions; TIM1_CH3N_1 is available by remap.
20 PB2 bidirectional General-purpose I/O that also latches the BOOT1 boot-mode select value.
21 PB10 bidirectional GPIO with I2C2_SCL and USART3_TX alternate functions; TIM2_CH3_1 is available by remap.
22 PB11 bidirectional GPIO with I2C2_SDA and USART3_RX alternate functions; TIM2_CH4_1 is available by remap.
23 VSS_1 power_in Digital ground pin for the I/O and core domain.
24 VDD_1 power_in Digital supply pin, 2.7 V to 5.5 V, for I/O pins, RC oscillators, reset block and internal regulator.
25 PB12 bidirectional GPIO with SPI2_NSS, I2C2_SMBAI, USART3_CK and TIM1_BKIN alternate functions.
26 PB13 bidirectional GPIO with SPI2_SCK, USART3_CTS and TIM1_CH1N alternate functions.
27 PB14 bidirectional GPIO with SPI2_MISO, USART3_RTS and TIM1_CH2N alternate functions.
28 PB15 bidirectional GPIO with SPI2_MOSI and TIM1_CH3N alternate functions.
29 PA8 bidirectional GPIO with USART1_CK, TIM1_CH1 and MCO clock output alternate functions.
30 PA9 bidirectional GPIO with USART1_TX and TIM1_CH2 alternate functions.
31 PA10 bidirectional GPIO with USART1_RX and TIM1_CH3 alternate functions.
32 PA11 bidirectional Analog-capable GPIO with USART1_CTS, USBHDM and TIM1_CH4 alternate functions.
33 PA12 bidirectional Analog-capable GPIO with USART1_RTS, USBHDP and TIM1_ETR alternate functions.
34 PA13 bidirectional Default SWDIO serial-wire debug pin after reset on the C8T6 part; can be reconfigured as PA13 by software.
35 VSS_2 power_in Digital ground pin.
36 VDD_2 power_in Digital supply pin, 2.7 V to 5.5 V.
37 PA14 bidirectional Default SWCLK serial-wire debug clock pin after reset on the C8T6 part; can be reconfigured as PA14 by software.
38 PA15 bidirectional GPIO with TIM2_CH1_1, TIM2_ETR_1 and SPI1_NSS_1 remapped alternate functions.
39 PB3 bidirectional GPIO with TIM2_CH2_1 and SPI1_SCK_1 remapped alternate functions.
40 PB4 bidirectional GPIO with TIM3_CH1_1 and SPI1_MISO_1 remapped alternate functions.
41 PB5 bidirectional GPIO with I2C1_SMBAI, TIM3_CH2_1 and SPI1_MOSI_1 alternate functions.
42 PB6 bidirectional Analog-capable GPIO with I2C1_SCL and TIM4_CH1 alternate functions; USART1_TX_1 is available by remap.
43 PB7 bidirectional Analog-capable GPIO with I2C1_SDA and TIM4_CH2 alternate functions; USART1_RX_1 is available by remap.
44 BOOT0 input Boot-mode select input (TTL/CMOS Schmitt level) that, together with BOOT1, selects main flash, system memory or internal SRAM boot at startup.
45 PB8 bidirectional Analog-capable GPIO with TIM4_CH3 alternate function; I2C1_SCL_1 is available by remap.
46 PB9 bidirectional Analog-capable GPIO with TIM4_CH4 alternate function; I2C1_SDA_1 is available by remap.
47 VSS_3 power_in Digital ground pin.
48 VDD_3 power_in Digital supply pin, 2.7 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer WCH Jiangsu Qin Heng
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating ambient temperature TA -40 85 ℃ 19
Storage ambient temperature TS -40 105 ℃ 19
External main supply voltage (VDD and VDDA) VDD-VSS -0.3 5.5 V 19
Input voltage on any pin VIN 5.5 V 19
Voltage difference between different supply pins /ΔVDDx/ 50 mV 19
Voltage difference between different ground pins /VSSx-VSS/ 50 mV 19
ESD voltage (human body model) VESD(HBM) 4000 V 19
Total current through VDD/VDDA supply lines IVDD 50 mA 19
Total current through VSS ground line IVss 50 mA 19
Sink current on any I/O and control pin IIO -25 mA 19
Output current on any I/O and control pin IIO 25 mA 19
Internal system clock frequency FSYSCLK 80 MHz 20
Standard operating voltage VDD 2.7 5.5 V 20
Analog supply voltage (ADC not used) VDDA 2.7 5.5 V ADC not used; must equal VDD 20
Analog supply voltage (ADC used) VDDA 3 5.5 V ADC used 20
Backup domain operating voltage VBAT 1.8 5.5 V must not exceed VDD 20
Ambient operating temperature TA -40 85 ℃ 20
VDD rising slew rate tVDD 0 us/V VDD rising 20
VDD falling slew rate tVDD 30 us/V VDD falling 20
Internal reference voltage VREFINT 1.12 1.28 V TA = -40℃～85℃ 20
ADC sampling time for internal reference voltage read TS_vrefint 0.107 17.1 1/fADC slow sampling recommended 20
External high-speed clock frequency FHSE_ext 8 25 MHz 23
External low-speed clock frequency FLSE_ext 32.768 1000 KHz 23
Crystal/resonator frequency (HSE) FOSC_IN 4 8 16 MHz 24
HSI duty cycle DuCyHSI 45 50 55 % 24
HSI oscillator accuracy ACCHSI -1.8 1.8 % TA = 0℃～70℃ 24
HSI oscillator accuracy ACCHSI -2.5 2.5 % TA = -40℃～85℃ 24
LSI frequency FLSI 25 36 60 KHz 25
LSI duty cycle DuCyLSI 45 50 55 % 25
PLL input clock frequency FPLL_IN 4 8 16 MHz 25
PLL input clock duty cycle PLL duty 40 60 % 25
Page (128 byte) programming time tERASE_128 2.4 2.75 3.2 ms TA = -40℃～85℃ 25
Page (128 byte) erase time tERASE 2.4 2.75 3.2 ms TA = -40℃～85℃ 25
16-bit programming time tprog 2.4 2.75 3.2 ms TA = -40℃～85℃ 25
Page (1K byte) erase time tERASE 19 22 26 ms TA = -40℃～85℃ 25
Full chip erase time tME 2.4 2.75 3.2 ms TA = -40℃～85℃ 25
Flash programming voltage Vprog 2.7 5.5 V 25
Standard I/O input low voltage (TTL port) VIL -0.3 0.8 V TTL port 26
Standard I/O input low voltage (CMOS port) VIL -0.3 0.8 V CMOS port 26
Input leakage current Ilkg -1 1 uA 26
Weak pull-up equivalent resistance RPU 30 42 55 KΩ 26
Weak pull-down equivalent resistance RPD 30 42 55 KΩ 26
Output low voltage, single pin sink (TTL port) VOL 0.4 V TTL port, IIO = +8mA, 2.7V< VDD <5.5V 26
Output low voltage, single pin sink (CMOS port) VOL 0.4 V CMOS port, IIO = +8mA, 2.7V< VDD <5.5V 26
Output high voltage, single pin source (CMOS port) VOH 2.3 V 26
Output low voltage, single pin sink VOL 1.3 V IIO = +20mA, 2.7V< VDD <5.5V 26
NRST input low voltage VIL(NRST) -0.3 0.8 V 27
NRST weak pull-up equivalent resistance RPU 30 42 55 KΩ 27
Timer external clock frequency (CH1 to CH4) FEXT 0 MHz 27
Timer external clock frequency (CH1 to CH4) FEXT 0 36 MHz fTIMxCLK = 72MHz 27
16-bit counter clock period tCOUNTER 0.0139 910 us fTIMxCLK = 72MHz 28
Maximum possible count time tMAX_COUNT 59.6 s fTIMxCLK = 72MHz 28
SCL low-level time (standard I2C) tw(SCKL) 4.7 us standard I2C 28
SCL low-level time (fast I2C) tw(SCKL) 1.2 us fast I2C 28
SCL high-level time (standard I2C) tw(SCKH) 4 us standard I2C 28
SCL high-level time (fast I2C) tw(SCKH) 0.6 us fast I2C 28
SDA data setup time (standard I2C) tSU(SDA) 250 ns standard I2C 28
SDA data setup time (fast I2C) tSU(SDA) 100 ns fast I2C 28

CAD (KiCad official)

  • Symbol: CH32V103C8T6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ch32v103c8t6-etched.step / ch32v103c8t6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch32v103c8t6.step / ch32v103c8t6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH Jiangsu Qin Heng datasheet (36 pp, sha256 51d2a9f352d2275e, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF