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CH32V003J4M6
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WCH Jiangsu Qin Heng Microcontrollers (MCU/MPU/SOC), SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCH32V003J4M6
WCH Jiangsu Qin Heng · Microcontrollers (MCU/MPU/SOC) · SOP-8
CH32V003J4M6 from WCH Jiangsu Qin Heng, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PD6 | bidirectional | I/O/A pin whose default function is PD6, with URX/A6 as its default multiplexed functions (A6 is ADC input channel 6) and T2CH3_3/UTX_2 as remap options. |
| 2 | VSS | power_in | Ground reference; the datasheet states all voltages are referenced to VSS. |
| 3 | PA2 | bidirectional | I/O/A pin whose default function is PA2, with A0/OPP0 and OSCO/T1CH2N as default multiplexed functions (A0 is ADC input channel 0). |
| 4 | VDD | power_in | Supply pin: VDD = 2.7 to 5.5 V powers the I/O pins and the internal regulator, and the datasheet notes ADC performance degrades below 2.9 V. |
| 5 | PC1 | bidirectional | 5 V-tolerant (FT) I/O whose default function is SDA/NSS, with URX_3 and T1BKIN_1/T2CH4_1 among its remap options. |
| 6 | PC2 | bidirectional | 5 V-tolerant (FT) I/O whose default function is SCL/URTS/T1BKIN, with AETR_1 and T2CH2_1 among its remap options. |
| 7 | PC4 | bidirectional | I/O/A pin whose default function is PC4, with T1CH4/MCO and A2 (ADC input channel 2) as default multiplexed functions. |
| 8 | PD1 | bidirectional | I/O/A pin whose default function is PD1 with SWIO (single-wire debug interface) as a default multiplexed function, plus T1CH3N and AETR2 alternates. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | WCH Jiangsu Qin Heng |
| Package | SOP-8 |
| Category | Embedded Processors & Controllers |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 工作时的环境温度 (operating ambient temperature) | TA | -40 | 85 | ℃ | 14 | ||
| 存储时的环境温度 (storage temperature) | TS | -40 | 125 | ℃ | 14 | ||
| 外部主供电电压 (VDD-VSS) | VDD-VSS | -0.3 | 5.5 | V | 14 | ||
| FT (5V-tolerant) pin input voltage | VIN | 5.5 | V | FT (5V-tolerant) pins | 14 | ||
| Voltage difference between VDD pins | /ΔVDD_x/ | 50 | mV | 14 | |||
| Voltage difference between VSS pins | /ΔVSS_x/ | 50 | mV | 14 | |||
| Total current through VDD power line (supply current) | IVDD | 100 | mA | 14 | |||
| Total current through VSS ground line (sink current) | IVSS | 80 | mA | 14 | |||
| Sink current on any I/O and control pin | IIO | 20 | mA | any I/O and control pin | 14 | ||
| Output current on any I/O and control pin | IIO | -20 | mA | any I/O and control pin | 14 | ||
| Injection current on HSE OSC_IN pin | IINJ(PIN) | -4 | 4 | mA | HSE OSC_IN pin | 14 | |
| Injection current on other pins | IINJ(PIN) | -4 | 4 | mA | other pins | 14 | |
| Total injection current on all I/O and control pins | ΣIINJ(PIN) | -20 | 20 | mA | all I/O and control pins | 14 | |
| Internal AHB clock frequency | FHCLK | 50 | MHz | 15 | |||
| Standard operating voltage VDD | VDD | 2.7 | 5.5 | V | ADC not used | 15 | |
| Standard operating voltage VDD | VDD | 2.8 | 5.5 | V | ADC used (recommended) | 15 | |
| Ambient temperature | TA | -40 | 85 | ℃ | 15 | ||
| Junction temperature range | TJ | -40 | 105 | ℃ | 15 | ||
| VDD rise rate | tVDD | 0 | us/V | VDD rising | 15 | ||
| VDD fall rate | tVDD | 20 | us/V | VDD falling | 15 | ||
| Power-on/power-down reset threshold (rising edge) | VPOR/PDR | 2.32 | 2.5 | 2.68 | V | rising edge | 15 |
| Power-on/power-down reset threshold (falling edge) | VPOR/PDR | 2.3 | 2.48 | 2.66 | V | falling edge | 15 |
| Power-on reset delay | tRSTTEMPO | 1 | 1.5 | 21 | mS | power-on reset | 15 |
| Internal reference voltage | VREFINT | 1.17 | 1.2 | 1.23 | V | TA = -40℃～85℃ | 16 |
| ADC sample time when reading internal reference voltage | TS_vrefint | 3 | 500 | 1/fADC | reading internal reference voltage | 16 | |
| Page (64 bytes) programming time | tERASE_64 | 2.4 | 3.1 | ms | TA = -20℃～85℃ | 19 | |
| Page (64 bytes) erase time | tERASE | 2.4 | 3.1 | ms | TA = -20℃～85℃ | 19 | |
| 16-bit programming time | tprog | 2.4 | 3.1 | ms | TA = -20℃～85℃ | 19 | |
| Full chip erase time | tME | 2.4 | 3.1 | ms | TA = -20℃～85℃ | 19 | |
| Programming voltage | Vprog | 2.8 | 5.5 | V | 19 | ||
| FT I/O pin input high-level voltage | VIH | 5.5 | V | FT I/O pin | 20 | ||
| Standard I/O pin input low-level voltage | VIL | -0.3 | V | standard I/O pin | 20 | ||
| FT I/O pin input low-level voltage | VIL | -0.3 | V | FT I/O pin | 20 | ||
| Weak pull-up equivalent resistance | RPU | 35 | 45 | 55 | kΩ | 20 | |
| Weak pull-down equivalent resistance | RPD | 35 | 45 | 55 | kΩ | 20 | |
| Output low-level voltage, 8 pins sinking (TTL port) | VOL | 0.4 | V | TTL port, IIO = +8mA, 2.7V< VDD <5.5V | 20 | ||
| Output low-level voltage, 8 pins sinking (CMOS port) | VOL | 0.4 | V | CMOS port, IIO = +8mA, 2.7V< VDD <5.5V | 20 | ||
| Output high-level voltage, 8 pins sourcing (CMOS port) | VOH | 2.3 | V | CMOS port, IIO = +8mA, 2.7V< VDD <5.5V | 20 | ||
| Output low-level voltage, 8 pins sinking (high-current) | VOL | 1.3 | V | IIO = +20mA | 20 | ||
| External reset NRST input low-level voltage | VIL(NRST) | -0.3 | V | 21 | |||
| NRST weak pull-up equivalent resistance | RPU | 35 | 45 | 55 | kΩ | 21 | |
| External high-speed clock frequency (HSE) | FHSE_ext | 4 | 24 | 25 | MHz | external clock | 18 |
| OSC_IN input low-level voltage | VHSEL | 0 | V | OSC_IN input | 18 | ||
| External clock duty cycle | DuTy(HSE) | 40 | 50 | 60 | % | 18 | |
| OSC_IN input leakage current | IL | -1 | 1 | uA | OSC_IN input | 18 | |
| Crystal/ceramic resonator frequency | FOSC_IN | 4 | 24 | 25 | MHz | crystal/ceramic resonator | 18 |
| HSI RC oscillator duty cycle | DuCyHSI | 45 | 50 | 55 | % | 19 | |
| HSI RC oscillator accuracy (calibrated) | ACCHSI | -1.2 | 1.6 | % | TA = 0℃～70℃ | 19 | |
| HSI RC oscillator accuracy (calibrated) | ACCHSI | -2.2 | 2.2 | % | TA = -40℃～85℃ | 19 | |
| HSI RC oscillator power consumption | IDD(HSI) | 120 | 180 | 270 | uA | 19 | |
| LSI RC oscillator frequency | FLSI | 100 | 128 | 150 | KHz | 19 | |
| LSI RC oscillator duty cycle | DuTyLSI | 45 | 50 | 55 | % | 19 | |
| OPA supply voltage | VDD | 2.8 | 5.5 | V | OPA | 27 | |
| OPA common-mode input voltage range | CMIR | 0 | V | OPA | 27 | ||
| OPA input offset voltage | VIOFFSET | -13 | 3 | 13 | mV | OPA | 27 |
| OPA resistive load | RLOAD | 4 | kΩ | OPA | 27 | ||
| OPA capacitive load | CLOAD | 50 | pF | OPA | 27 | ||
| OPA low saturation output voltage | VOLSAT | 5 | mV | RLOAD = 4kΩ, input 0 | 27 | ||
| ADC operating voltage VDD and clock frequency | fADC | 1 | 6 | MHz | VDD = 2.8 to 5.5V | 25 |
CAD (KiCad official)
- Symbol:
CH32V003J4M6 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ch32v003j4m6-etched.step/ch32v003j4m6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ch32v003j4m6.step/ch32v003j4m6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: WCH Jiangsu Qin Heng datasheet (31 pp, sha256
2c05b25a3ef9269c, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).