component

CH32F207VCT6

Public Made by Adom

by adom

WCH(Jiangsu Qin Heng) Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollerch32f207vct6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
ch32f207vct6 / README.md
History Download
Ray Publish 0.1.0 5e35f35 4d ago

CH32F207VCT6

WCH(Jiangsu Qin Heng) · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

CH32F207VCT6 from WCH(Jiangsu Qin Heng), in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional GPIO PE2, 5V tolerant (FT), alternate functions FSMC_A23 and remap TIM10_BKIN_2.
2 PE3 bidirectional GPIO PE3, 5V tolerant (FT), alternate functions FSMC_A19 and remap TIM10_CH1N_2.
3 PE4 bidirectional GPIO PE4, 5V tolerant (FT), alternate functions FSMC_A20 and remap TIM10_CH2N_2.
4 PE5 bidirectional GPIO PE5, 5V tolerant (FT), alternate functions FSMC_A21 and remap TIM10_CH3N_2.
5 PE6 bidirectional GPIO PE6, 5V tolerant (FT), alternate function FSMC_A22.
6 VBAT power_in Battery supply of 1.8~3.6V that powers the RTC, external low-frequency oscillator and backup registers when VDD is off.
7 PC13/TAMPER-RTC bidirectional GPIO PC13 / TAMPER-RTC powered via the backup power switch; as output limited to one pin at a time, 2MHz, 30pF max, 3mA source limit.
8 PC14/OSC32IN bidirectional GPIO PC14 / OSC32_IN low-speed 32.768kHz oscillator input, powered via backup power switch (3mA limit as output).
9 PC15/OSC32OUT bidirectional GPIO PC15 / OSC32_OUT low-speed 32.768kHz oscillator output, powered via backup power switch (3mA limit as output).
10 VSS_5 power_in Ground for the VDD supply domain (VSS_5).
11 VDD_5 power_in System power supply VDD, 2.4~3.6V, for some I/O pins and the internal voltage regulator.
12 OSC_IN input High-speed external 3~25MHz oscillator input (PD0 remap on smaller packages).
13 OSC_OUT output High-speed external 3~25MHz oscillator output (PD1 remap on smaller packages).
14 NRST input External reset input.
15 PC0 bidirectional GPIO PC0 with analog input ADC_IN10; alternates TIM9_CH1N, UART6_TX, ETH_RGMII_RXC.
16 PC1 bidirectional GPIO PC1 with analog input ADC_IN11; alternates TIM9_CH2N, UART6_RX, ETH MDC/RGMII_RXCTL.
17 PC2 bidirectional GPIO PC2 with analog input ADC_IN12; alternates TIM9_CH3N, UART7_TX, OPA3_CH1N, ETH_MII_TXD2.
18 PC3 bidirectional GPIO PC3 with analog input ADC_IN13; alternates TIM10_CH3, UART7_RX, OPA4_CH1N, ETH_MII_TX_CLK.
19 VSSA power_in Analog ground.
20 VREF- power_in Negative ADC/DAC reference voltage input.
21 VREF+ power_in Positive ADC/DAC reference voltage input.
22 VDDA power_in Analog supply 2.4~3.6V for HSI RC analog part, ADC, temperature sensor, DAC and PLL; must equal VIO and be at least 2.4V when using ADC.
23 PA0/WKUP/ADC0 bidirectional GPIO PA0 with WKUP wake-up, ADC_IN0, USART2_CTS, TIM2_CH1/ETR, TIM5_CH1, TIM8_ETR.
24 PA1/ADC1 bidirectional GPIO PA1 with ADC_IN1, USART2_RTS, TIM2_CH2, TIM5_CH2, OPA3_OUT0, ETH_MII_RX_CLK.
25 PA2/ADC2 bidirectional GPIO PA2 with ADC_IN2, USART2_TX, TIM2_CH3, TIM5_CH3, TIM9_CH1, OPA2_OUT0, ETH MDIO.
26 PA3/ADC3 bidirectional GPIO PA3 with ADC_IN3, USART2_RX, TIM2_CH4, TIM5_CH4, TIM9_CH2, OPA1_OUT0, ETH_MII_COL.
27 VSS_4 power_in Ground for the VDD supply domain (VSS_4).
28 VDD_4 power_in System power supply VDD, 2.4~3.6V (VDD_4).
29 PA4/ADC4/DAC0 bidirectional GPIO PA4 with ADC_IN4, DAC output 1, SPI1_NSS/SPI3_NSS, USART2_CK, DVP_HSYNC.
30 PA5/ADC5/DAC1 bidirectional GPIO PA5 with ADC_IN5, DAC output 2, SPI1_SCK, DVP_VSYNC, OPA2_CH1N.
31 PA6/ADC6 bidirectional GPIO PA6 with ADC_IN6, SPI1_MISO, TIM3_CH1, DVP_PCLK, OPA1_CH1N.
32 PA7/ADC7 bidirectional GPIO PA7 with ADC_IN7, SPI1_MOSI, TIM3_CH2, OPA2_CH1P, ETH_MII_RX_DV.
33 PC4/ADC14 bidirectional GPIO PC4 with ADC_IN14, TIM9_CH4, UART8_TX, OPA4_CH1P, ETH_MII_RXD0.
34 PC5/ADC15 bidirectional GPIO PC5 with ADC_IN15, TIM9_BKIN, UART8_RX, OPA3_CH1P, ETH_MII_RXD1.
35 PB0/ADC8 bidirectional GPIO PB0 with ADC_IN8, TIM3_CH3, TIM8_CH2N, UART4_TX_1, OPA1_CH1P, ETH_MII_RXD2.
36 PB1/ADC9 bidirectional GPIO PB1 with ADC_IN9, TIM3_CH4, TIM8_CH3N, UART4_RX_1, OPA4_CH0N, ETH_MII_RXD3.
37 PB2/BOOT1 bidirectional GPIO PB2, 5V tolerant, doubles as BOOT1 boot-mode select; also OPA3_CH0N.
38 PE7 bidirectional GPIO port E pin PE7.
39 PE8 bidirectional GPIO port E pin PE8.
40 PE9 bidirectional GPIO port E pin PE9.
41 PE10 bidirectional GPIO port E pin PE10.
42 PE11 bidirectional GPIO port E pin PE11.
43 PE12 bidirectional GPIO port E pin PE12.
44 PE13 bidirectional GPIO port E pin PE13.
45 PE14 bidirectional GPIO port E pin PE14.
46 PE15 bidirectional GPIO port E pin PE15.
47 PB10 bidirectional GPIO PB10 with I2C2_SCL, USART3_TX, OPA2_CH0N, ETH_MII_RX_ER, TIM2_CH3 remap.
48 PB11 bidirectional GPIO PB11 with I2C2_SDA, USART3_RX, OPA1_CH0N, ETH_MII_TX_EN, TIM2_CH4 remap.
49 VSS_1 power_in Ground for the VIO supply domain (VSS_1).
50 VIO_1 power_in I/O supply 2.4~3.6V for most I/O pins and the Ethernet module; must not exceed VDD.
51 PB12 bidirectional GPIO PB12 with SPI2_NSS/I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OPA4_CH0P.
52 PB13 bidirectional GPIO PB13 with SPI2_SCK/I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, OPA3_CH0P.
53 PB14 bidirectional GPIO PB14 with SPI2_MISO, USART3_RTS, TIM1_CH2N, OPA2_CH0P.
54 PB15 bidirectional GPIO PB15 with SPI2_MOSI/I2S2_SD, TIM1_CH3N, OPA1_CH0P.
55 PD8 bidirectional GPIO port D pin PD8.
56 PD9 bidirectional GPIO port D pin PD9.
57 PD10 bidirectional GPIO port D pin PD10.
58 PD11 bidirectional GPIO port D pin PD11.
59 PD12 bidirectional GPIO port D pin PD12.
60 PD13 bidirectional GPIO port D pin PD13.
61 PD14 bidirectional GPIO port D pin PD14.
62 PD15 bidirectional GPIO port D pin PD15.
63 PC6/RXP bidirectional GPIO PC6 with TIM8_CH1, I2S2_MCK, SDIO_D6 and ETH_RXP (10M PHY receive positive).
64 PC7/RXN bidirectional GPIO PC7 with TIM8_CH2, I2S3_MCK, SDIO_D7 and ETH_RXN (10M PHY receive negative).
65 PC8/TXP bidirectional GPIO PC8 with TIM8_CH3, SDIO_D0, DVP_D2 and ETH_TXP (10M PHY transmit positive).
66 PC9/TXN bidirectional GPIO PC9 with TIM8_CH4, SDIO_D1, DVP_D3 and ETH_TXN (10M PHY transmit negative).
67 PA8 bidirectional GPIO PA8, 5V tolerant, with USART1_CK, TIM1_CH1 and MCO clock output.
68 PA9 bidirectional GPIO PA9, 5V tolerant, with USART1_TX, TIM1_CH2, OTG_FS_VBUS, DVP_D0.
69 PA10 bidirectional GPIO PA10, 5V tolerant, with USART1_RX, TIM1_CH3, OTG_FS_ID, DVP_D1.
70 PA11/USB1DM bidirectional GPIO PA11 with USB1 D- (OTG_FS_DM/USBDM), USART1_CTS, CAN1_RX, TIM1_CH4.
71 PA12/USB1DP bidirectional GPIO PA12 with USB1 D+ (OTG_FS_DP/USBDP), USART1_RTS, CAN1_TX, TIM1_ETR.
72 PA13/SWDIO bidirectional GPIO PA13, default SWDIO serial debug data pin, 5V tolerant.
73 NC unconnected No connection.
74 VSS_2 power_in Ground for the VDD supply domain (VSS_2).
75 VDD_2 power_in System power supply VDD, 2.4~3.6V (VDD_2).
76 PA14/SWCLK bidirectional GPIO PA14, default SWCLK serial debug clock pin, 5V tolerant.
77 PA15 bidirectional GPIO PA15, 5V tolerant, with SPI3_NSS/I2S3_WS, SPI1_NSS, TIM2_CH1_ETR remap, UART8_RX_1.
78 PC10 bidirectional GPIO PC10, 5V tolerant, with UART4_TX, SDIO_D2, DVP_D8, SPI3_SCK/I2S3_CK.
79 PC11 bidirectional GPIO PC11, 5V tolerant, with UART4_RX, SDIO_D3, DVP_D4, SPI3_MISO.
80 PC12 bidirectional GPIO PC12, 5V tolerant, with UART5_TX, SDIO_CK, DVP_D9, SPI3_MOSI/I2S3_SD.
81 PD0 bidirectional GPIO PD0 (analog capable), 5V tolerant, with FSMC_D2 and CAN1_RX.
82 PD1 bidirectional GPIO PD1 (analog capable), 5V tolerant, with FSMC_D3 and CAN1_TX.
83 PD2 bidirectional GPIO PD2, 5V tolerant, with TIM3_ETR, UART5_RX, SDIO_CMD, DVP_D11.
84 PD3 bidirectional GPIO PD3, 5V tolerant, with FSMC_CLK and USART2_CTS remap.
85 PD4 bidirectional GPIO PD4, 5V tolerant, with FSMC_NOE and USART2_RTS remap.
86 PD5 bidirectional GPIO PD5, 5V tolerant, with FSMC_NWE and USART2_TX remap.
87 PD6 bidirectional GPIO PD6, 5V tolerant, with FSMC_NWAIT, DVP_D10 and USART2_RX remap.
88 PD7 bidirectional GPIO PD7, 5V tolerant, with FSMC_NE1/NCE2 and USART2_CK remap.
89 PB3 bidirectional GPIO PB3, 5V tolerant, with SPI3_SCK/I2S3_CK, TRACESWO, TIM2_CH2 remap, SPI1_SCK.
90 PB4 bidirectional GPIO PB4, 5V tolerant, with SPI3_MISO, TIM3_CH1 remap, SPI1_MISO, UART5_TX_1.
91 PB5 bidirectional GPIO PB5 (not 5V tolerant) with I2C1_SMBA, SPI3_MOSI/I2S3_SD, ETH PPS_OUT, SPI1_MOSI, CAN2_RX.
92 PB6/USB2DM bidirectional GPIO PB6, 5V tolerant, with I2C1_SCL, TIM4_CH1, USBHD_DM/USBHS_DM (USB2 D-), DVP_D5.
93 PB7/USB2DP bidirectional GPIO PB7, 5V tolerant, with I2C1_SDA, FSMC_NADV, TIM4_CH2, USBHD_DP/USBHS_DP (USB2 D+).
94 BOOT0 input Boot-mode select input BOOT0 (with BOOT1 selects flash, system memory or SRAM boot).
95 PB8 bidirectional GPIO PB8 (analog capable), 5V tolerant, with TIM4_CH3, SDIO_D4, DVP_D6, I2C1_SCL, CAN1_RX.
96 PB9 bidirectional GPIO PB9 (analog capable), 5V tolerant, with TIM4_CH4, SDIO_D5, DVP_D7, I2C1_SDA, CAN1_TX.
97 PE0 bidirectional GPIO PE0, 5V tolerant, with TIM4_ETR and FSMC_NBL0.
98 PE1 bidirectional GPIO PE1, 5V tolerant, with FSMC_NBL1 and UART4_RX_2.
99 VSS_3 power_in Ground for the VIO supply domain (VSS_3).
100 VIO_3 power_in I/O supply 2.4~3.6V for most I/O pins and the Ethernet module; must not exceed VDD.

Key specifications

Parameter Value
Manufacturer WCH(Jiangsu Qin Heng)
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature during operation TA -40 85 ℃ 49
Ambient temperature during storage TS -40 125 ℃ 49
External main supply voltage (including VDDA and VDD) VDD-VSS -0.3 4 V 49
IO domain supply voltage VIO-VSS -0.3 4 V 49
Input voltage on FT (5V tolerant) pin VIN 5.5 V FT pin 49
Variations between different main power supply pins /ΔVDD_x/ 50 mV 49
Variations between different IO power supply pins /ΔVIO_x/ 50 mV 49
Variations between different ground pins /ΔVSS_x/ 50 mV 49
Total current into VDD/VDDA power lines (source) IVDD 150 mA 49
Total current out of VSS ground lines (sink) IVss 150 mA 50
Sink current on any I/O and control pin IIO 25 mA Sink 50
Output current on any I/O and control pin IIO -25 mA Output 50
Injected current on other pins IINJ(PIN) -5 5 mA 50
Total injected current on all IOs and control pins ΣIINJ(PIN) -25 25 mA 50
Internal AHB clock frequency FHCLK 144 MHz 50
Internal APB1 clock frequency FPCLK1 144 MHz 50
Internal APB2 clock frequency FPCLK2 144 MHz 50
Standard operating voltage VDD 2.4 3.6 V 50
Standard operating voltage, USB or ETH VDD 3 3.6 V Use USB or ETH 50
Output voltage on most IO pins VIO 2.4 3.6 V VIO cannot be more than VDD 50
Analog operating voltage VDDA 2.4 3.6 V VDDA must be the same as VIO 50
Backup operating voltage VBAT 1.8 3.6 V Cannot be more than VDD 50
Ambient temperature TA -40 85 ℃ 50
Junction temperature range TJ -40 85 ℃ 50
VDD fall time rate tVDD 30 us/V VDD fall time rate 50
Power-on/power-down reset threshold, rising edge VPOR/PDR 1.9 2.2 2.4 V Rising edge 51
Power-on/power-down reset threshold, falling edge VPOR/PDR 1.9 2.2 2.4 V Falling edge 51
PVD hysteresis VPVDhyst 0.08 V 51
PDR hysteresis VPDRhyst 20 mV 51
Reset time, power on reset tRSTTEMPO 24 28 30 mS Power on reset 51
Reset time, other resets tRSTTEMPO 8 10 30 mS Other resets 51
Internal reference voltage VREFINT 1.17 1.2 1.23 V TA = -40℃～85℃ 51
Supply current in Run mode, all peripherals enabled IDD 31.2 mA External clock FHCLK = 144MHz, all peripherals enabled 52
Supply current in Run mode, all peripherals disabled IDD 19.3 mA External clock FHCLK = 144MHz, all peripherals disabled 52
External high-speed clock frequency FHSE_ext 3 8 25 MHz 57
OSC_IN input leakage current IL -1 1 uA 58
External low-speed clock frequency FLSE_ext 32.768 1000 kHz 58
HSI frequency FHSI 8 MHz 59
HSI accuracy ACCHSI -1 1.6 % TA = 0℃～70℃ 60
HSI accuracy ACCHSI -2.2 2.2 % TA = -40℃～85℃ 60
LSI frequency FLSI 25 39 60 kHz 60
PLL input clock FPLL_IN 3 8 25 MHz 60
PLL multiplier output clock FPLL_OUT 18 144 MHz 60
PLL lock time tLOCK 200 us 60
Programming voltage Vprog 2.4 3.6 V 61
Flash data retention tRET 20 year 61
Weak pull-up equivalent resistance RPU 30 40 55 kΩ 62
Weak pull-down equivalent resistance RPD 30 40 55 kΩ 62
Output low level, TTL port VOL 0.4 V TTL port, IIO = +8mA, 2.7V< VDD <3.6V 62
Output high level, CMOS port VOH 2.3 V CMOS port, IIO = +8mA, 2.7V< VDD <3.6V 62
ADC supply voltage VDDA 2.4 3.6 V 78
ADC clock frequency fADC 14 MHz 78
Temperature sensor average slope Avg_Slope 3.8 4.3 4.7 mV/℃ 80
Temperature sensor voltage at 25℃ V25 1.34 1.4 1.46 V 80
DAC supply voltage VDDA 2.4 3.3 3.6 V 80

CAD (KiCad official)

  • Symbol: CH32F207VCT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: ch32f207vct6-etched.step / ch32f207vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch32f207vct6.step / ch32f207vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH(Jiangsu Qin Heng) datasheet (86 pp, sha256 f6363e3b6e70c3ee, retrieved 2026-10-24, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF