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CH32F203VCT6

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WCH(Jiangsu Qin Heng) Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CH32F203VCT6

WCH(Jiangsu Qin Heng) · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

CH32F203VCT6 from WCH(Jiangsu Qin Heng), in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5V-tolerant (FT) I/O with default function PE2, alternate FSMC_A23, and remap TIM10_BKIN_2.
2 PE3 bidirectional 5V-tolerant (FT) I/O with default function PE3, alternate FSMC_A19, and remap TIM10_CH1N_2.
3 PE4 bidirectional 5V-tolerant (FT) I/O with default function PE4, alternate FSMC_A20, and remap TIM10_CH2N_2.
4 PE5 bidirectional 5V-tolerant (FT) I/O with default function PE5, alternate FSMC_A21, and remap TIM10_CH3N_2.
5 PE6 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_A22; the table prints PE5 as the default name for this pin.
6 VBAT power_in Backup power input (1.8-3.6V) that independently powers the RTC, the external low-speed oscillator and backup registers when VDD is off.
7 PC13 bidirectional I/O powered through the power switch that can absorb only 3mA; as output it is limited to 2MHz, 30pF max load, and must not drive current sources such as LEDs, with TAMPER-RTC function.
8 PC14 bidirectional Analog-capable I/O powered through the 3mA power switch (same output limits as PC13) and used as OSC32_IN for the low-speed oscillator.
9 PC15 bidirectional Analog-capable I/O powered through the 3mA power switch (same output limits as PC13) and used as OSC32_OUT for the low-speed oscillator.
10 VSS_5 power_in Digital ground pin.
11 VDD_5 power_in Digital supply pin; VDD is specified as 2.4-3.6V and powers some I/O pins and the internal voltage regulator.
12 OSC_IN input High-speed external oscillator input for the 3-25MHz HSE, with remap to PD0.
13 OSC_OUT output High-speed external oscillator output for the 3-25MHz HSE, with remap to PD1.
14 NRST input External reset input; an external reset on NRST is listed as an exit condition from Stop and Standby modes.
15 PC0 bidirectional Analog-capable I/O with ADC_IN10 and TIM9_CH1N, UART6_TX, ETH_RGMII_RXC alternate functions.
16 PC1 bidirectional Analog-capable I/O with ADC_IN11 and TIM9_CH2N, UART6_RX, ETH_MII_MDC alternate functions.
17 PC2 bidirectional Analog-capable I/O with ADC_IN12 and TIM9_CH3N, UART7_TX, OPA3_CH1N alternate functions.
18 PC3 bidirectional Analog-capable I/O with ADC_IN13 and TIM10_CH3, UART7_RX, OPA4_CH1N alternate functions.
19 VSSA power_in Analog ground pin for the ADC, DAC, temperature sensor and PLL.
20 VREF- power_in ADC/DAC reference negative pin; the extracted pages give no voltage limit for this pin.
21 VREF+ power_in ADC/DAC reference positive pin; the extracted pages give no voltage limit for this pin.
22 VDDA power_in Analog supply for the high-frequency RC oscillator, ADC, temperature sensor, DAC and PLL; VDDA is 2.4-3.6V and must equal VI/O, and must be at least 2.4V when using the ADC.
23 PA0 bidirectional 5V-tolerant (FT) I/O with WKUP wake-up input, ADC_IN0, and alternate TIM2_CH1, TIM2_ETR, USART2_CTS.
24 PA1 bidirectional 5V-tolerant (FT) I/O with ADC_IN1 and alternate TIM2_CH2, TIM5_CH2, USART2_RTS.
25 PA2 bidirectional 5V-tolerant (FT) I/O with ADC_IN2 and alternate TIM2_CH3, TIM5_CH3, USART2_TX.
26 PA3 bidirectional 5V-tolerant (FT) I/O with ADC_IN3 and alternate TIM2_CH4, TIM5_CH4, USART2_RX.
27 VSS_4 power_in Digital ground pin.
28 VDD_4 power_in Digital supply pin; VDD is specified as 2.4-3.6V.
29 PA4 bidirectional 5V-tolerant (FT) I/O with ADC_IN4, DAC_OUT1, and alternate SPI1_NSS, USART2_CK, SPI3_NSS/I2S3_WS.
30 PA5 bidirectional 5V-tolerant (FT) I/O with ADC_IN5, DAC_OUT2, and alternate SPI1_SCK, DVP_VSYNC, OPA2_CH1N.
31 PA6 bidirectional 5V-tolerant (FT) I/O with ADC_IN6 and alternate SPI1_MISO, TIM8_BKIN, TIM3_CH1, DVP_PCLK.
32 PA7 bidirectional 5V-tolerant (FT) I/O with ADC_IN7 and alternate SPI1_MOSI, TIM8_CH1N, TIM3_CH2, OPA2_CH1P.
33 PC4 bidirectional Analog-capable I/O with ADC_IN14 and alternate TIM9_CH4, UART8_TX, OPA4_CH1P.
34 PC5 bidirectional Analog-capable I/O with ADC_IN15 and alternate TIM9_BKIN, UART8_RX, OPA3_CH1P.
35 PB0 bidirectional Analog-capable I/O with ADC_IN8 and alternate TIM3_CH3, TIM8_CH2N, OPA1_CH1P.
36 PB1 bidirectional Analog-capable I/O with ADC_IN9 and alternate TIM3_CH4, TIM8_CH3N, OPA4_CH0N.
37 PB2 bidirectional 5V-tolerant (FT) I/O shared with BOOT1, with alternate OPA3_CH0N and TIM9_CH3N_1.
38 PE7 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D4, OPA3_OUT1, TIM1_ETR_3.
39 PE8 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D5, OPA4_OUT1, TIM1_CH1N_3, UART5_TX_2.
40 PE9 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D6, TIM1_CH1_3, UART5_RX_2.
41 PE10 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D7, TIM1_CH2N_3, UART6_TX_2.
42 PE11 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D8, TIM1_CH2_3, UART6_RX_2.
43 PE12 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D9, TIM1_CH3N_3, UART7_TX_2.
44 PE13 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D10, TIM1_CH3_3, UART7_RX_2.
45 PE14 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D11, OPA2_OUT1, TIM1_CH4_3, UART8_TX_2.
46 PE15 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D12, OPA1_OUT1, TIM1_BKIN_3, UART8_RX_2.
47 PB10 bidirectional 5V-tolerant (FT) I/O with alternate I2C2_SCL, USART3_TX, OPA2_CH0N, TIM2_CH3_2.
48 PB11 bidirectional 5V-tolerant (FT) I/O with alternate I2C2_SDA, USART3_RX, OPA1_CH0N, TIM2_CH4_2.
49 VSS_1 power_in Digital ground pin.
50 VIO_1 power_in I/O supply for most GPIO pins; VI/O is 2.4-3.6V and must not be higher than VDD during operation.
51 PB12 bidirectional 5V-tolerant (FT) I/O with alternate SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX.
52 PB13 bidirectional 5V-tolerant (FT) I/O with alternate SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX.
53 PB14 bidirectional 5V-tolerant (FT) I/O with alternate SPI2_MISO, TIM1_CH2N, USART3_RTS, OPA2_CH0P.
54 PB15 bidirectional 5V-tolerant (FT) I/O with alternate SPI2_MOSI/I2S2_SD, TIM1_CH3N/OPA1_CH0P, USART1_TX_2.
55 PD8 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D13, USART3_TX_3, TIM9_CH1N_2.
56 PD9 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D14, USART3_RX_3, TIM9_CH1_ETR_2.
57 PD10 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D15, USART3_CK_3, TIM9_CH2N_2.
58 PD11 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_A16, USART3_CTS_3, TIM9_CH2_2.
59 PD12 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_A17, TIM4_CH1_1, TIM9_CH3N_2, USART3_RTS_3.
60 PD13 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_A18, TIM4_CH2_1, TIM9_CH3_2.
61 PD14 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D0, TIM4_CH3_1, TIM9_BKIN_2.
62 PD15 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D1, TIM4_CH4_1, TIM9_CH4_2.
63 PC6/RXP bidirectional 5V-tolerant (FT) I/O with alternate I2S2_MCK, TIM8_CH1, SDIO_D6, TIM3_CH1_3; the VCT6 figure labels this pin RXP.
64 PC7/RXN bidirectional 5V-tolerant (FT) I/O with alternate I2S3_MCK, TIM8_CH2, SDIO_D7, TIM3_CH2_3; the VCT6 figure labels this pin RXN.
65 PC8/TXP bidirectional 5V-tolerant (FT) I/O with alternate TIM8_CH3, SDIO_D0, DVP_D2, TIM3_CH3_3; the VCT6 figure labels this pin TXP.
66 PC9/TXN bidirectional 5V-tolerant (FT) I/O with alternate TIM8_CH4, SDIO_D1, DVP_D3, TIM3_CH4_3; the VCT6 figure labels this pin TXN.
67 PA8 bidirectional 5V-tolerant (FT) I/O with alternate USART1_CK, TIM1_CH1, and MCO clock output.
68 PA9 bidirectional 5V-tolerant (FT) I/O with alternate USART1_TX, TIM1_CH2, OTG_FS_VBUS, DVP_D0.
69 PA10 bidirectional 5V-tolerant (FT) I/O with alternate USART1_RX, TIM1_CH3, OTG_FS_ID, DVP_D1.
70 PA11 bidirectional 5V-tolerant (FT) I/O with alternate USART1_CTS, USBDM/OTG_FS_DM, CAN1_RX, TIM1_CH4.
71 PA12 bidirectional 5V-tolerant (FT) I/O with alternate USART1_RTS, USBDP/OTG_FS_DP, CAN1_TX, TIM1_ETR.
72 PA13 bidirectional 5V-tolerant (FT) I/O; default function is SWDIO serial-wire debug data, with alternate TIM10_CH2N and TIM8_CH1N_1.
73 NC unconnected No internal connection on this pin per the VCT6 pin arrangement; the pin definition table marks it as unused.
74 VSS_2 power_in Digital ground pin.
75 VDD_2 power_in Digital supply pin; VDD is specified as 2.4-3.6V.
76 PA14 bidirectional 5V-tolerant (FT) I/O; default function is SWCLK serial-wire debug clock, with alternate TIM10_CH3N, TIM8_CH2N_1, UART8_TX_1.
77 PA15 bidirectional 5V-tolerant (FT) I/O with alternate SPI3_NSS/I2S3_WS, TIM2_CH1_ETR_1, SPI1_NSS, UART8_RX_1, TIM8_CH3N_1.
78 PC10 bidirectional 5V-tolerant (FT) I/O with alternate UART4_TX, SDIO_D2, TIM10_ETR, DVP_D8, USART3_TX_1, SPI3_SCK.
79 PC11 bidirectional 5V-tolerant (FT) I/O with alternate UART4_RX, SDIO_D3, TIM10_CH4, DVP_D4, USART3_RX_1, SPI3_MISO.
80 PC12 bidirectional 5V-tolerant (FT) I/O with alternate UART5_TX, SDIO_CK, TIM10_BKIN, DVP_D9, USART3_CK_1, SPI3_MOSI.
81 PD0 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D2, CAN1_RX, TIM10_ETR_2; on LQFP100 PD0 is an inherent function pin and does not need software reconfiguration.
82 PD1 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_D3, CAN1_TX, TIM10_CH1_2; on LQFP100 PD1 is an inherent function pin.
83 PD2 bidirectional 5V-tolerant (FT) I/O with alternate TIM3_ETR, UART5_RX, SDIO_CMD, DVP_D11.
84 PD3 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_CLK, USART2_CTS_1, TIM10_CH2_2.
85 PD4 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_NOE and USART2_RTS_1.
86 PD5 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_NWE, USART2_TX_1, TIM10_CH3_2.
87 PD6 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_NWAIT, DVP_D10, USART2_RX_1.
88 PD7 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_NE1, FSMC_NCE2, USART2_CK_1, TIM10_CH4_2.
89 PB3 bidirectional I/O with alternate SPI3_SCK/I2S3_CK, TRACESWO, TIM2_CH2_1, SPI1_SCK, TIM10_CH1_1.
90 PB4 bidirectional I/O with alternate SPI3_MISO, TIM3_CH1_2, SPI1_MISO, UART5_TX_1, TIM10_CH2_1.
91 PB5 bidirectional I/O with alternate I2C1_SMBA, SPI3_MOSI/I2S3_SD, TIM3_CH2_2, SPI1_MOSI, CAN2_RX, UART5_RX_1.
92 PB6 bidirectional 5V-tolerant (FT) I/O with alternate I2C1_SCL, TIM4_CH1, USBFS_DM, DVP_D5, USART1_TX_1, CAN2_TX.
93 PB7 bidirectional 5V-tolerant (FT) I/O with alternate I2C1_SDA, FSMC_NADV, TIM4_CH2, USBFS_DP, USART1_RX_1, TIM8_CH2_1.
94 BOOT0 input Boot-mode select input; together with BOOT1 (PB2) it selects boot from program flash, system memory or internal SRAM.
95 PB8 bidirectional 5V-tolerant (FT) I/O with alternate TIM4_CH3, SDIO_D4, TIM10_CH1, DVP_D6, I2C1_SCL, CAN1_RX.
96 PB9 bidirectional 5V-tolerant (FT) I/O with alternate TIM4_CH4, SDIO_D5, TIM10_CH2, DVP_D7, I2C1_SDA, CAN1_TX.
97 PE0 bidirectional 5V-tolerant (FT) I/O with alternate TIM4_ETR, FSMC_NBL0, TIM4_ETR_1, UART4_TX_2.
98 PE1 bidirectional 5V-tolerant (FT) I/O with alternate FSMC_NBL1 and UART4_RX_2.
99 VSS_3 power_in Digital ground pin.
100 VIO_3 power_in I/O supply for most GPIO pins; VI/O is 2.4-3.6V and must not be higher than VDD during operation.

Key specifications

Parameter Value
Manufacturer WCH(Jiangsu Qin Heng)
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature during operation TA -40 85 ℃ 35
Ambient temperature during storage TS -40 125 ℃ 35
External main supply voltage (including VDDA and VDD) VDD-VSS -0.3 4 V 35
I/O domain supply voltage VIO-VSS -0.3 4 V 35
Input voltage on the FT (5V tolerance) pin VIN 5.5 V FT (5V tolerance) pin 35
Variations between different main power supply pins /△VDD_x/ 50 mV 35
Variations between different I/O power supply pins /△VIO_x/ 50 mV 35
Total current into VDD/VDDA/VI/O power lines (supply current) IVDD 150 mA 36
Total current out of VSS ground lines (outflow current) IVss 150 mA 36
Sink current on any I/O and control pin II/O 25 mA 36
Output current on any I/O and control pin II/O -25 mA 36
Injected current on NRST pin IINJ(PIN) -5 5 mA 36
Injected current on HSE's OSC_IN pin and LSE's OSC_IN pin IINJ(PIN) -5 5 mA 36
Total injected current on all I/Os and control pins ∑IINJ(PIN) -25 25 mA 36
Standard operating voltage VDD 2.4 3.6 V Standard operating voltage 36
Operating voltage when using USB or ETH VDD 3 3.6 V Use USB or ETH 36
Output voltage on most I/O pins VI/O 2.4 3.6 V VI/O cannot be more than VDD 36
Analog operating voltage VDDA 2.4 3.6 V ADC is not used 36
Backup operating voltage VBAT 1.8 3.6 V Cannot be more than VDD 36
Ambient temperature TA -40 85 ℃ 36
Junction temperature range TJ -40 85 ℃ 36
VDD rise time rate tVDD 0 us/V 36
VDD fall time rate 30 us/V 36
Power-on/power-down reset threshold (rising edge) VPOR/PDR 1.9 2.2 2.4 V Rising edge 37
Power-on/power-down reset threshold (falling edge) VPOR/PDR 1.9 2.2 2.4 V Falling edge 37
Power on reset timeout tRSTTEMPO 24 28 30 mS Power on reset 37
Other resets timeout tRSTTEMPO 8 10 30 mS Other resets 37
Internal reference voltage VREFINT 1.17 1.2 1.23 V TA = -40℃～85℃ 37
External clock frequency (HSE) FHSE_ext 3 8 25 MHz 41
OSC_IN input leakage current IL -1 1 uA 41
User external clock frequency (LSE) FLSE_ext 32.768 1000 KHz 42
OSC32_IN input leakage current IL -1 1 uA 42
Resonator frequency FOSC_IN 3 8 25 MHz 42
Duty cycle (HSI) DuCyHSI 45 50 55 % 43
Accuracy of HSI oscillator (after calibration) ACCHSI -1 1.6 % TA = 0℃～70℃ 43
Accuracy of HSI oscillator (after calibration) ACCHSI -2.2 2.2 % TA = -40℃～85℃ 43
HSI oscillator power consumption IDD(HSI) 120 180 270 uA 44
Frequency (LSI) FLSI 25 39 60 KHz 44
PLL input clock FPLL_IN 3 8 25 MHz 44
Offset error EO -2 2 LSB fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 3.3V 63
Average slope (negative temperature coefficient) Avg_Slope 3.8 4.3 4.7 mV/℃ 64
Voltage at 25℃ V25 1.34 1.4 1.46 V 64
Measurement range of temperature sensor after software calibration ATSC -12 12 ℃ after software calibration 64
Standard I/O pin, input low-level voltage VIL -0.3 V Standard I/O pin 45
FT I/O pin, input low-level voltage VIL -0.3 V FT I/O pin 45
FT I/O pin, input high level voltage VIH 5.5 V FT I/O pin 45
Weak pull-up equivalent resistance RPU 30 40 55 kΩ 45
Weak pull-down equivalent resistance RPD 30 40 55 kΩ 45
Output low level when 8 pins are sunk (TTL port) VOL 0.4 V TTL port, II/O = +8mA, 2.7V< VDD <3.6V 46
Output low level when 8 pins are sunk (CMOS port) VOL 0.4 V CMOS port, II/O = +8mA, 2.7V< VDD <3.6V 46
Output high level when 8 pins are sourced (CMOS port) VOH 2.3 V 46
Output low level when 8 pins are sunk VOL 1.3 V II/O = +20mA, 2.7V< VDD <3.6V 46
Output low level when 8 pins are sunk VOL 0.4 V II/O = +6mA, 2.4V< VDD <2.7V 46
NRST input low-level voltage VIL(NRST) -0.3 V 47
Weak pull-up equivalent resistance (NRST) RPU 30 40 55 kΩ 47
Timer external clock frequency on CH1 to CH4 FEXT 0 36 MHz fTIMxCLK = 72MHz 47
16-bit counter clock cycle when the internal clock is selected tCOUNTER 1 65536 tTIMxCLK Internal clock selected 47
SDA data setup time tSU(SDA) 250 ns Standard I2C 48
SDA data setup time tSU(SDA) 100 ns Fast I2C 48
SPI SCK high and low time tw(SCKH)/tw(SCKL) 40 60 ns Master mode, fPCLK = 36MHz, Prescaler factor = 4 49

CAD (KiCad official)

  • Symbol: CH32F203VCT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: ch32f203vct6-etched.step / ch32f203vct6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch32f203vct6.step / ch32f203vct6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH(Jiangsu Qin Heng) datasheet (69 pp, sha256 4b7f09894a062d50, retrieved 2026-10-25, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF