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CH32F203CBT6

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WCH Jiangsu Qin Heng Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CH32F203CBT6

WCH Jiangsu Qin Heng · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

CH32F203CBT6 from WCH Jiangsu Qin Heng, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Backup supply of 1.8-3.6V that independently powers the RTC, the external low-frequency oscillator and the backup registers when VDD is turned off.
2 PC13/TAMPER-RTC bidirectional GPIO powered through the power switch, which can only absorb 3mA; when used as an output only one of PC13-PC15 may be an output at a time, only in 2MHz mode, with a maximum load of 30pF and no current-source use.
3 PC14/OSC32_IN bidirectional GPIO powered through the backup power switch (3mA limit shared with PC13/PC15, 2MHz output mode, 30pF max load) that doubles as the 32.768 kHz low-speed oscillator input OSC32_IN.
4 PC15/OSC32_OUT bidirectional GPIO powered through the backup power switch (3mA limit shared with PC13/PC14, 2MHz output mode, 30pF max load) that doubles as the low-speed oscillator output OSC32_OUT.
5 OSC_IN/PD0 input High-speed external oscillator input (3-25MHz) that is OSC_IN by default after reset and can be reconfigured as PD0 by software.
6 OSC_OUT/PD1 output High-speed external oscillator output that is OSC_OUT by default after reset and can be reconfigured as PD1 by software.
7 NRST input External reset input on NRST; an external reset on this pin also exits Stop and Standby modes.
8 VSSA power_in Analog ground for the analog circuitry (ADC, DAC, temperature sensor, PLL and high-frequency RC oscillator).
9 VDDA power_in Analog supply of 2.4-3.6V for the high-frequency RC oscillator, ADC, temperature sensor, DAC and PLL, which must equal VI/O and be at least 2.4V when the ADC is used.
10 PA0/WKUP/ADC0 bidirectional GPIO with WKUP wake-up function (rising edge on WKUP wakes from Standby), ADC_IN0 analog input, and timer and USART2_CTS alternate functions.
11 PA1/ADC1 bidirectional GPIO with ADC_IN1 analog input and alternate functions including USART2_RTS, TIM5_CH2 and TIM2_CH2.
12 PA2/ADC2 bidirectional GPIO with ADC_IN2 analog input and alternate functions including USART2_TX, TIM5_CH3, TIM2_CH3 and TIM9_CH1.
13 PA3/ADC3 bidirectional GPIO with ADC_IN3 analog input and alternate functions including USART2_RX, TIM5_CH4, TIM2_CH4 and TIM9_CH2.
14 PA4/ADC4/DAC0 bidirectional GPIO with ADC_IN4 analog input and DAC_OUT1 analog output, plus alternate functions including SPI1_NSS, USART2_CK, SPI3_NSS and I2S3_WS.
15 PA5/ADC5/DAC1 bidirectional GPIO with ADC_IN5 analog input and DAC_OUT2 analog output, plus alternate functions including SPI1_SCK and DVP_VSYNC.
16 PA6/ADC6 bidirectional GPIO with ADC_IN6 analog input, plus alternate functions including SPI1_MISO, TIM8_BKIN, TIM3_CH1 and DVP_PCLK.
17 PA7/ADC7 bidirectional GPIO with ADC_IN7 analog input, plus alternate functions including SPI1_MOSI, TIM8_CH1N, TIM3_CH2 and ETH_MII_RX_DV.
18 PB0/ADC8 bidirectional GPIO with ADC_IN8 analog input, plus alternate functions including TIM3_CH3, TIM8_CH2N, OPA1_CH1P and ETH_MII_RXD2.
19 PB1/ADC9 bidirectional GPIO with ADC_IN9 analog input, plus alternate functions including TIM3_CH4, TIM8_CH3N, OPA4_CH0N and ETH_MII_RXD3.
20 PB2/BOOT1 bidirectional 5V-tolerant (FT) GPIO that also serves as the BOOT1 boot-mode input, and is pulled down internally when used as BOOT1 on devices without this pin.
21 PB10 bidirectional 5V-tolerant (FT) GPIO with I2C2_SCL, USART3_TX, OPA2_CH0N, ETH_MII_RX_ER and TIM2_CH3/TIM10_BKIN alternate functions.
22 PB11 bidirectional 5V-tolerant (FT) GPIO with I2C2_SDA, USART3_RX, OPA1_CH0N, ETH_MII_TX_EN and TIM2_CH4/TIM10_ETR alternate functions.
23 VSS_1 power_in Ground pin for the I/O domain.
24 VDD_I/O_1 power_in I/O supply of 2.4-3.6V that powers most I/O pins and sets their output high level; it must not be higher than VDD during operation.
25 PB12 bidirectional 5V-tolerant (FT) GPIO with SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, OPA4_CH0P, CAN2_RX and ETH_MII_TXD0 alternate functions.
26 PB13 bidirectional 5V-tolerant (FT) GPIO with SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, OPA3_CH0P, CAN2_TX and ETH_MII_TXD1 alternate functions.
27 PB14 bidirectional 5V-tolerant (FT) GPIO with SPI2_MISO, TIM1_CH2N, USART3_RTS and OPA2_CH0P alternate functions.
28 PB15 bidirectional 5V-tolerant (FT) GPIO with SPI2_MOSI/I2S2_SD, TIM1_CH3N/OPA1_CH0P and USART1_TX_2 alternate functions.
29 PA8 bidirectional 5V-tolerant (FT) GPIO with USART1_CK, TIM1_CH1 and MCO (microcontroller clock output) alternate functions.
30 PA9 bidirectional 5V-tolerant (FT) GPIO with USART1_TX, TIM1_CH2, OTG_FS_VBUS and DVP_D0 alternate functions.
31 PA10 bidirectional 5V-tolerant (FT) GPIO with USART1_RX, TIM1_CH3, OTG_FS_ID and DVP_D1 alternate functions.
32 PA11/USB1DM bidirectional 5V-tolerant (FT) GPIO with USB full-speed D- (USBDM) and OTG_FS_DM, plus USART1_CTS, CAN1_RX and TIM1_CH4 alternate functions.
33 PA12/USB1DP bidirectional 5V-tolerant (FT) GPIO with USB full-speed D+ (USBDP) and OTG_FS_DP, plus USART1_RTS, CAN1_TX and TIM1_ETR alternate functions.
34 PA13/SWDIO bidirectional 5V-tolerant (FT) serial-wire debug data pin SWDIO, enabled by default after power-on or reset, with TIM10_CH2N and TIM8_CH1N_1 alternate functions.
35 VSS_2 power_in Ground pin for the digital supply domain.
36 VDD_2 power_in System digital supply of 2.4-3.6V that powers some I/O pins and the internal voltage regulator.
37 PA14/SWCLK bidirectional 5V-tolerant (FT) serial-wire debug clock SWCLK, enabled by default after power-on or reset, with TIM10_CH3N, TIM8_CH2N_1 and UART8_TX_1 alternate functions.
38 PA15 bidirectional 5V-tolerant (FT) GPIO with SPI3_NSS, I2S3_WS, TIM2_CH1_ETR, SPI1_NSS, TIM8_CH3N_1 and UART8_RX_1 alternate functions.
39 PB3 bidirectional 5V-tolerant (FT) GPIO with SPI3_SCK, I2S3_CK, TRACESWO, TIM2_CH2_1 and SPI1_SCK alternate functions.
40 PB4 bidirectional 5V-tolerant (FT) GPIO with SPI3_MISO, TIM3_CH1_2, SPI1_MISO, UART5_TX_1 and TIM10_CH2_1 alternate functions.
41 PB5 bidirectional GPIO with I2C1_SMBA, SPI3_MOSI, I2S3_SD, ETH_MII_PPS_OUT, SPI1_MOSI and CAN2_RX alternate functions; the table gives no FT (5V-tolerant) rating for this pin.
42 PB6 bidirectional 5V-tolerant (FT) GPIO with I2C1_SCL, TIM4_CH1, USBFS_DM/USBHS_DM, DVP_D5, USART1_TX_1 and CAN2_TX alternate functions.
43 PB7 bidirectional 5V-tolerant (FT) GPIO with I2C1_SDA, FSMC_NADV, TIM4_CH2, USBFS_DP/USBHS_DP, USART1_RX_1 and TIM8_CH2_1 alternate functions.
44 BOOT0 input Boot-mode select input that is sampled at startup together with BOOT1 (PB2) to choose boot from program flash, system memory or internal SRAM.
45 PB8 bidirectional 5V-tolerant (FT) GPIO with TIM4_CH3, SDIO_D4, TIM10_CH1, DVP_D6, I2C1_SCL, CAN1_RX and UART6_TX_1 alternate functions.
46 PB9 bidirectional 5V-tolerant (FT) GPIO with TIM4_CH4, SDIO_D5, TIM10_CH2, DVP_D7, I2C1_SDA, CAN1_TX and UART6_RX_1 alternate functions.
47 VSS_3 power_in Ground pin for the I/O domain.
48 VDD_I/O_3 power_in I/O supply of 2.4-3.6V that powers most I/O pins and sets their output high level; it must not be higher than VDD during operation.

Key specifications

Parameter Value
Manufacturer WCH Jiangsu Qin Heng
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Ambient temperature during operation TA -40 85 ℃ 35
Ambient temperature during storage TS -40 125 ℃ 35
External main supply voltage (including VDDA and VDD) VDD-VSS -0.3 4 V 35
I/O domain supply voltage VIO-VSS -0.3 4 V 35
Input voltage on the FT (5V tolerance) pin VIN 5.5 V 35
Variations between different main power supply pins /△VDD_x/ 50 mV 35
Variations between different I/O power supply pins /△VIO_x/ 50 mV 35
Variations between different ground pins /△VSS_x/ 50 mV 36
Total current into VDD/VDDA/VI/O power lines (supply current) IVDD 150 mA 36
Total current out of VSS ground lines (outflow current) IVss 150 mA 36
Sink current on any I/O and control pin II/O 25 mA 36
Output current on any I/O and control pin II/O -25 mA 36
Injected current on NRST pin IINJ(PIN) -5 5 mA 36
Injected current on HSE's OSC_IN pin and LSE's OSC_IN pin IINJ(PIN) -5 5 mA 36
Injected current on other pins IINJ(PIN) -5 5 mA 36
Total injected current on all I/Os and control pins ∑IINJ(PIN) -25 25 mA 36
Internal AHB clock frequency FHCLK 144 MHz 36
Internal APB1 clock frequency FPCLK1 144 MHz 36
Internal APB2 clock frequency FPCLK2 144 MHz 36
Standard operating voltage VDD 2.4 3.6 V 36
Standard operating voltage VDD 3 3.6 V Use USB or ETH 36
Output voltage on most I/O pins VI/O 2.4 3.6 V VI/O cannot be more than VDD 36
Analog operating voltage (ADC is not used) VDDA 2.4 3.6 V VDDA must be the same as VI/O 36
Backup operating voltage VBAT 1.8 3.6 V Cannot be more than VDD 36
Ambient temperature TA -40 85 ℃ 36
Junction temperature range TJ -40 85 ℃ 36
VDD fall time rate tVDD 30 us/V 36
VDD rise time rate tVDD 0 us/V 36
Power-on/power-down reset threshold, rising edge VPOR/PDR 1.9 2.2 2.4 V Rising edge 37
Power-on/power-down reset threshold, falling edge VPOR/PDR 1.9 2.2 2.4 V Falling edge 37
Power on reset time tRSTTEMPO 24 28 30 mS Power on reset 37
Other resets time tRSTTEMPO 8 10 30 mS Other resets 37
Internal reference voltage VREFINT 1.17 1.2 1.23 V TA = -40℃~85℃ 37
External clock frequency FHSE_ext 3 8 25 MHz 41
OSC_IN input pin low-level voltage VHSEL 0 V 41
OSC_IN input leakage current IL -1 1 uA 41
User external clock frequency FLSE_ext 32.768 1000 KHz 42
OSC32_IN input leakage current IL -1 1 uA 42
Resonator frequency FOSC_IN 3 8 25 MHz 42
Duty cycle HSI DuCyHSI 45 50 55 % 43
Accuracy of HSI oscillator (after calibration) ACCHSI -1 1.6 % TA = 0℃～70℃ 43
Accuracy of HSI oscillator (after calibration) ACCHSI -2.2 2.2 % TA = -40℃～85℃ 43
Frequency FLSI 25 39 60 KHz 44
Duty cycle LSI DuCyLSI 45 50 55 % 44
HSI oscillator power consumption IDD(HSI) 120 180 270 uA 44
PLL input clock FPLL_IN 3 8 25 MHz 44
PLL input clock duty cycle 40 60 % 44
PLL multiplier output clock FPLL_OUT 18 144 MHz 44
VCO output clock (PLL2 and PLL3) FVCO 60 150 MHz 44
Programming frequency Fprog 60 MHz TA = -40℃～85℃ 45
Programming voltage Vprog 2.4 3.6 V 45
FT I/O pin, input high level voltage VIH 5.5 V 45
Standard I/O pin, input low-level voltage VIL -0.3 V 45
FT I/O pin, input low-level voltage VIL -0.3 V 45
Weak pull-up equivalent resistance RPU 30 40 55 kΩ 45
Weak pull-down equivalent resistance RPD 30 40 55 kΩ 45
Output low level when 8 pins are sunk VOL 0.4 V CMOS port, II/O = +8mA 2.7V< VDD <3.6V 46
Output low level when 8 pins are sunk VOL 1.3 V II/O = +20mA 2.7V< VDD <3.6V 46
Output high level when 8 pins are sourced VOH 2.3 V 46

CAD (KiCad official)

  • Symbol: CH32F203CBT6
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ch32f203cbt6-etched.step / ch32f203cbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ch32f203cbt6.step / ch32f203cbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: WCH Jiangsu Qin Heng datasheet (69 pp, sha256 4b7f09894a062d50, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF