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CESDLC5V0K5
Public Made by Adomby adom
Changjing ESD And Surge Protection (TVS/ESD), SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCESDLC5V0K5
Changjing · ESD And Surge Protection (TVS/ESD) · SOT-363
CESDLC5V0K5 from Changjing, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | ESD-protected line at the bottom of the schematic, with a uni-directional TVS to the common node; VRWM 5V, clamping 13V at IPP=2.5A (8/20µs), CJ 10pF typ at VR=0V, 1MHz. |
| 2 | GND | power_in | Common ground/reference node of the array, to which all protected I/O lines clamp; ESD ratings are per channel (I/O to GND). |
| 3 | I/O2 | passive | ESD-protected line at the bottom of the schematic, with a uni-directional TVS to the common node; VRWM 5V, clamping 13V at IPP=2.5A (8/20µs), CJ 10pF typ at VR=0V, 1MHz. |
| 4 | I/O3 | passive | ESD-protected line at the top of the schematic, with a uni-directional TVS to the common node; VRWM 5V, clamping 13V at IPP=2.5A (8/20µs), CJ 10pF typ at VR=0V, 1MHz. |
| 5 | I/O4 | passive | ESD-protected line at the top of the schematic, with a uni-directional TVS to the common node; VRWM 5V, clamping 13V at IPP=2.5A (8/20µs), CJ 10pF typ at VR=0V, 1MHz. |
| 6 | I/O5 | passive | ESD-protected line at the top of the schematic, with a uni-directional TVS to the common node; VRWM 5V, clamping 13V at IPP=2.5A (8/20µs), CJ 10pF typ at VR=0V, 1MHz. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Changjing |
| Package | SOT-363 |
| Category | Circuit Protection |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| IEC 61000-4-2 ESD Voltage Air Model | VESD(1) | -8 | 8 | kV | Ten non-repetitive ESD pulses, per channel (I/O to GND) | 2 | |
| IEC 61000-4-2 ESD Voltage Contact Model | VESD(1) | -8 | 8 | kV | Ten non-repetitive ESD pulses, per channel (I/O to GND) | 2 | |
| JESD22-A114-B ESD Voltage Per Human Body Model | -8 | 8 | 2 | ||||
| ESD Voltage Machine Model | -0.4 | 0.4 | 2 | ||||
| Peak Pulse Power | PPP(2) | 33 | W | Non-repetitive 8/20µs pulse, IEC61000-4-5 | 2 | ||
| Peak Pulse Current | IPP(2) | 2.5 | A | Non-repetitive 8/20µs pulse, IEC61000-4-5 | 2 | ||
| Lead Solder Temperature - Maximum | TL | 260 | ℃ | 10 second duration | 2 | ||
| Operation Junction and Storage Temperature Range | TJ,Tstg | -55 | 150 | ℃ | 2 | ||
| Breakdown voltage | V(BR) | 6.2 | 7.2 | V | IT=1mA | 3 | |
| Reverse stand off voltage | VRWM | 5 | V | 3 | |||
| Reverse leakage current | IR | 1 | µA | VRWM=5V | 3 | ||
| Forward voltage | VF | 0.9 | V | IF=10mA | 3 | ||
| Clamping voltage | VC | 13 | V | IPP=2.5A | 3 | ||
| Junction capacitance | CJ | 10 | 12 | pF | VR=0V, f=1MHz | 3 |
CAD (KiCad official)
- Symbol:
CESDLC5V0K5 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SOT-363 (KiCad packages3D, STEP)
- 3D model files:
cesdlc5v0k5-etched.step/cesdlc5v0k5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cesdlc5v0k5.step/cesdlc5v0k5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Changjing datasheet (6 pp, sha256
f5bbf5f1af23b28b, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).