component
CEP9060N
Public Made by Adomby adom
CET(Chino-Excel Tech) MOSFETs, TO-220. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Publish 0.1.0
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CEP9060N
CET(Chino-Excel Tech) · MOSFETs · TO-220
CEP9060N from CET(Chino-Excel Tech), in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate, with an absolute maximum gate-source voltage of ±20 V and a gate threshold voltage of 2 V min to 4 V max at VDS = VGS, ID = 250 µA. |
| 2 | D | passive | Drain, rated for 55 V drain-source voltage, 90 A continuous drain current and 360 A pulsed drain current. |
| 3 | S | passive | Source, which also carries the body-diode current of up to 62 A with a maximum forward voltage of 1.3 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CET(Chino-Excel Tech) |
| Package | TO-220 |
| Category | Transistors |
| Pins | 3 |
CAD (KiCad official)
- Symbol:
CEP9060N - Footprint:
Package_TO_SOT_THT:TO-220-3_Vertical - 3D model: TO-220 (KiCad packages3D, STEP)
- 3D model files:
cep9060n-etched.step/cep9060n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cep9060n.step/cep9060n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: CET(Chino-Excel Tech) datasheet (4 pp, sha256
7a779d5c55d8c865, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CEP9060N
**CET(Chino-Excel Tech)** · MOSFETs · TO-220
CEP9060N from CET(Chino-Excel Tech), in a TO-220. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate, with an absolute maximum gate-source voltage of ±20 V and a gate threshold voltage of 2 V min to 4 V max at VDS = VGS, ID = 250 µA. |
| 2 | D | passive | Drain, rated for 55 V drain-source voltage, 90 A continuous drain current and 360 A pulsed drain current. |
| 3 | S | passive | Source, which also carries the body-diode current of up to 62 A with a maximum forward voltage of 1.3 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | CET(Chino-Excel Tech) |
| Package | TO-220 |
| Category | Transistors |
| Pins | 3 |
## CAD (KiCad official)
- Symbol: `CEP9060N`
- Footprint: `Package_TO_SOT_THT:TO-220-3_Vertical`
- 3D model: TO-220 (KiCad packages3D, STEP)
- 3D model files: `cep9060n-etched.step` / `cep9060n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cep9060n.step` / `cep9060n.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [CET(Chino-Excel Tech) datasheet](docs/cep9060n-datasheet.pdf) (4 pp, sha256 `7a779d5c55d8c865`, retrieved 2026-10-28, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cep9060n-datasheet.pdf)