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cdcvf25081dr-etched.step	cdcvf25081dr: factory component page (tier=mfr) · Ray	1d ago
cdcvf25081dr-hero.glb	cdcvf25081dr: hero GLB from the etched model (keeps the MPN mark) · Ray	1d ago
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README.md	Initial commit: component/cdcvf25081dr · Ray	1d ago

CDCVF25081DR

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · SOIC-16

CDCVF25081DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLKIN	input	Clock input that must have a fixed frequency and phase for the PLL to acquire lock, and a stabilization time is required after power-up and application of a valid signal.
2	1Y0	output	Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor.
3	1Y1	output	Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor.
4	VDD	power_in	3.3-V power supply for output channels and core voltage, with a recommended supply range of 3 V to 3.6 V.
5	GND	power_in	Ground; connect the ground pad to system ground.
6	2Y0	output	Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor.
7	2Y1	output	Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor.
8	S2	input	Input selection pin that, together with S1, selects the input port and output mode (PLL, PLL bypass, or high impedance) as listed in Table 8-2.
9	S1	input	Input selection pin that, together with S2, selects the input port and output mode (PLL, PLL bypass, or high impedance) as listed in Table 8-2.
10	2Y2	output	Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor.
11	2Y3	output	Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor.
12	GND	power_in	Ground; connect the ground pad to system ground.
13	VDD	power_in	3.3-V power supply for output channels and core voltage, with a recommended supply range of 3 V to 3.6 V.
14	1Y2	output	Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor.
15	1Y3	output	Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor.
16	FBIN	input	Feedback input that must be wired to one of the outputs to complete the internal PLL loop, giving nominally zero delay from CLKIN to the outputs.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Clock/Timing
Pins	16

CAD (KiCad official)

Symbol: CDCVF25081DR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: cdcvf25081dr-etched.step / cdcvf25081dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcvf25081dr.step / cdcvf25081dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (26 pp, sha256 9f846462bdac0c0a, retrieved 2026-10-08, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF