component
CDCVF25081DR
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+52@@ -0,0 +1,52 @@+# CDCVF25081DR++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · SOIC-16++CDCVF25081DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLKIN | input | Clock input that must have a fixed frequency and phase for the PLL to acquire lock, and a stabilization time is required after power-up and application of a valid signal. |+| 2 | 1Y0 | output | Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor. |+| 3 | 1Y1 | output | Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor. |+| 4 | VDD | power_in | 3.3-V power supply for output channels and core voltage, with a recommended supply range of 3 V to 3.6 V. |+| 5 | GND | power_in | Ground; connect the ground pad to system ground. |+| 6 | 2Y0 | output | Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor. |+| 7 | 2Y1 | output | Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor. |+| 8 | S2 | input | Input selection pin that, together with S1, selects the input port and output mode (PLL, PLL bypass, or high impedance) as listed in Table 8-2. |+| 9 | S1 | input | Input selection pin that, together with S2, selects the input port and output mode (PLL, PLL bypass, or high impedance) as listed in Table 8-2. |+| 10 | 2Y2 | output | Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor. |+| 11 | 2Y3 | output | Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor. |+| 12 | GND | power_in | Ground; connect the ground pad to system ground. |+| 13 | VDD | power_in | 3.3-V power supply for output channels and core voltage, with a recommended supply range of 3 V to 3.6 V. |+| 14 | 1Y2 | output | Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor. |+| 15 | 1Y3 | output | Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor. |+| 16 | FBIN | input | Feedback input that must be wired to one of the outputs to complete the internal PLL loop, giving nominally zero delay from CLKIN to the outputs. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Clock/Timing |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CDCVF25081DR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cdcvf25081dr-etched.step` / `cdcvf25081dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcvf25081dr.step` / `cdcvf25081dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcvf25081.pdf) (26 pp, sha256 `9f846462bdac0c0a`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcvf25081dr-datasheet.pdf)
page.jsonadded+248@@ -0,0 +1,248 @@+{+ "slug": "cdcvf25081dr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdcvf25081dr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdcvf25081dr.kicad_sym",+ "cdcvf25081dr.kicad_mod",+ "cdcvf25081dr.glb",+ "cdcvf25081dr.step",+ "cdcvf25081dr.lbr",+ "docs/hero.png",+ "docs/cdcvf25081dr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cdcvf25081dr-hero.glb",+ "cdcvf25081dr-hero.overlay.json"+ ],+ "component": {+ "mpn": "CDCVF25081DR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cdcvf25081.pdf",+ "parts": {+ "symbol": "cdcvf25081dr.kicad_sym",+ "footprint": "cdcvf25081dr.kicad_mod",+ "model_3d": "cdcvf25081dr-hero.glb",+ "model_3d_plain": "cdcvf25081dr.glb",+ "model_3d_step": "cdcvf25081dr-etched.step",+ "model_3d_step_plain": "cdcvf25081dr.step",+ "lbr": "cdcvf25081dr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2862809",+ "digikey": "296-12270-2-ND",+ "mouser": "595-CDCVF25081DR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:28:47Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-12270-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CDCVF25081DR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLKIN",+ "type": "input",+ "description": "Clock input that must have a fixed frequency and phase for the PLL to acquire lock, and a stabilization time is required after power-up and application of a valid signal."+ },+ {+ "number": "2",+ "name": "1Y0",+ "type": "output",+ "description": "Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "3",+ "name": "1Y1",+ "type": "output",+ "description": "Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "4",+ "name": "VDD",+ "type": "power_in",+ "description": "3.3-V power supply for output channels and core voltage, with a recommended supply range of 3 V to 3.6 V."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; connect the ground pad to system ground."+ },+ {+ "number": "6",+ "name": "2Y0",+ "type": "output",+ "description": "Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "7",+ "name": "2Y1",+ "type": "output",+ "description": "Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "8",+ "name": "S2",+ "type": "input",+ "description": "Input selection pin that, together with S1, selects the input port and output mode (PLL, PLL bypass, or high impedance) as listed in Table 8-2."+ },+ {+ "number": "9",+ "name": "S1",+ "type": "input",+ "description": "Input selection pin that, together with S2, selects the input port and output mode (PLL, PLL bypass, or high impedance) as listed in Table 8-2."+ },+ {+ "number": "10",+ "name": "2Y2",+ "type": "output",+ "description": "Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "11",+ "name": "2Y3",+ "type": "output",+ "description": "Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "12",+ "name": "GND",+ "type": "power_in",+ "description": "Ground; connect the ground pad to system ground."+ },+ {+ "number": "13",+ "name": "VDD",+ "type": "power_in",+ "description": "3.3-V power supply for output channels and core voltage, with a recommended supply range of 3 V to 3.6 V."+ },+ {+ "number": "14",+ "name": "1Y2",+ "type": "output",+ "description": "Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "15",+ "name": "1Y3",+ "type": "output",+ "description": "Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor."+ },+ {+ "number": "16",+ "name": "FBIN",+ "type": "input",+ "description": "Feedback input that must be wired to one of the outputs to complete the internal PLL loop, giving nominally zero delay from CLKIN to the outputs."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout is taken from the D (SOIC-16) package entry in Table 5-1 and Figure 5-1; the datasheet's pin ; Pin types use KiCad ERC classes: datasheet 'P' (VDD) and 'G' (GND) are mapped to power_in as instruc"+ ],+ "pages_sent": 26,+ "cost_usd": 0.0881,+ "at": "2026-10-08T16:28:25"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cdcvf25081.pdf",+ "pages": 26,+ "sha256": "9f846462bdac0c0a",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdcvf25081dr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdcvf25081dr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d7fa5b1e824fe4a5b187b24537ac011f4acf5a5247fa6b6d492664683a21c953",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}