cdcvf2505dr

{
  "slug": "cdcvf2505dr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Clock Buffers, Drivers, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "rtc",
    "cdcvf2505dr"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cdcvf2505dr.kicad_sym",
    "cdcvf2505dr.kicad_mod",
    "cdcvf2505dr.glb",
    "cdcvf2505dr.step",
    "cdcvf2505dr.lbr",
    "docs/hero.png",
    "docs/cdcvf2505dr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cdcvf2505dr-etched.step"
  ],
  "visibility": {
    "public": true
  },
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "component": {
    "mpn": "CDCVF2505DR",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-8",
    "pin_count": 8,
    "category": "Clock Buffers, Drivers",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cdcvf2505.pdf",
    "parts": {
      "symbol": "cdcvf2505dr.kicad_sym",
      "footprint": "cdcvf2505dr.kicad_mod",
      "model_3d": "cdcvf2505dr-etched.glb",
      "model_3d_plain": "cdcvf2505dr.glb",
      "model_3d_step": "cdcvf2505dr-etched.step",
      "model_3d_step_plain": "cdcvf2505dr.step",
      "lbr": "cdcvf2505dr.lbr"
    },
    "pins": [
      {
        "number": "1",
        "name": "CLKIN",
        "type": "input",
        "description": "Reference clock input to the integrated PLL. Must have a fixed frequency (24 MHz to 200 MHz) and fixed phase for the PLL to obtain phase lock; a 100 µs stabilization time is required after a valid signal is applied. High-impedance CMOS input (0.7·VDD/0.3·VDD thresholds)."
      },
      {
        "number": "2",
        "name": "1Y1",
        "type": "output",
        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."
      },
      {
        "number": "3",
        "name": "1Y0",
        "type": "output",
        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."
      },
      {
        "number": "4",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference. Provide a low-inductance, low-resistance connection to the reference plane."
      },
      {
        "number": "5",
        "name": "1Y2",
        "type": "output",
        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."
      },
      {
        "number": "6",
        "name": "VDD",
        "type": "power_in",
        "description": "3.3-V supply (recommended 3.0-3.6 V; absolute max 4.3 V). Requires at least 100 nF local decoupling; a bank of 1 nF/2.2 nF/10 nF/47 nF/1 µF is recommended near the package."
      },
      {
        "number": "7",
        "name": "1Y3",
        "type": "output",
        "description": "Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz)."
      },
      {
        "number": "8",
        "name": "CLKOUT",
        "type": "output",
        "description": "Feedback output that closes the internal PLL loop; the feedback path is completed inside the chip and no external feedback wire is required. Can be loaded with a discrete capacitor (3-25 pF) to tune the phase relationship (zero delay, lead, or lag) between CLKIN and the 1Y[0-3] outputs. Not to be used to drive a signal trace."
      }
    ],
    "provenance": {
      "rebuilt": "component block rebuilt 2026-10-05 from this page's own README pinout table and .kicad_sym (pins cross-checked), no re-extraction"
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "distributor_links": {
      "digikey": "296-26040-2-ND",
      "mouser": "595-CDCVF2505DR"
    },
    "distributor_check": {
      "checked_at": "2026-10-05T18:55:37Z",
      "source": "Component Ocean /api/assign-pns + lcsc_map",
      "digikey": {
        "pn": "296-26040-2-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-CDCVF2505DR",
        "status": "found"
      }
    },
    "models_3d": [
      {
        "file": "cdcvf2505dr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cdcvf2505dr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d71af76f87db71a019af49cf9f3fb5366309abf5a3740bb9591dfb294da3ff24",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}