# CDCVF2505DR

**Texas Instruments** · Clock Buffers, Drivers · SOIC-8

CDCVF2505DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLKIN | input | Reference clock input to the integrated PLL. Must have a fixed frequency (24 MHz to 200 MHz) and fixed phase for the PLL to obtain phase lock; a 100 µs stabilization time is required after a valid signal is applied. High-impedance CMOS input (0.7·VDD/0.3·VDD thresholds). |
| 2 | 1Y1 | output | Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz). |
| 3 | 1Y0 | output | Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz). |
| 4 | GND | power_in | Device ground reference. Provide a low-inductance, low-resistance connection to the reference plane. |
| 5 | 1Y2 | output | Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz). |
| 6 | VDD | power_in | 3.3-V supply (recommended 3.0-3.6 V; absolute max 4.3 V). Requires at least 100 nF local decoupling; a bank of 1 nF/2.2 nF/10 nF/47 nF/1 µF is recommended near the package. |
| 7 | 1Y3 | output | Low-skew clock output copy of CLKIN with an integrated 25-Ω series damping resistor. Drives up to ±12 mA (VDD = 3 V). Tri-stated when the input clock is absent (≤1 MHz). |
| 8 | CLKOUT | output | Feedback output that closes the internal PLL loop; the feedback path is completed inside the chip and no external feedback wire is required. Can be loaded with a discrete capacitor (3-25 pF) to tune the phase relationship (zero delay, lead, or lag) between CLKIN and the 1Y[0-3] outputs. Not to be used to drive a signal trace. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | RTC |
| Pins | 8 |

## Ordering variants

- `CDCVF2505DRD`
- `CDCVF2505DR`
- `CDCVF2505DRDG4`
- `CDCVF2505DRG4`
- `CDCVF2505DRD.A`
- `CDCVF2505DR.A`
- `CDCVF2505DRPW`
- `CDCVF2505DRPWR`
- `CDCVF2505DRPWRG4`
- `CDCVF2505DRPW.A`
- `CDCVF2505DRPWR.A`

## CAD (KiCad official)

- Symbol: `CDCVF2505DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `cdcvf2505dr-etched.step` / `cdcvf2505dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcvf2505dr.step` / `cdcvf2505dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcvf2505.pdf) (None pp, sha256 `cb7590012710844f`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cdcvf2505dr-datasheet.pdf)