component

CDCVF2310MPWEP

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timingcdcvf2310mpwepfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers cdcvf2310mpwep: viewers · Ray 2d ago
cdcvf2310mpwep-etched.glb cdcvf2310mpwep: factory component page (tier=lcsc) · Ray 2d ago
cdcvf2310mpwep-etched.step cdcvf2310mpwep: factory component page (tier=lcsc) · Ray 2d ago
cdcvf2310mpwep-hero.glb cdcvf2310mpwep: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
cdcvf2310mpwep-hero.overlay.json Publish 0.1.0 · Ray 2d ago
cdcvf2310mpwep.glb Publish 0.1.0 · Ray 2d ago
cdcvf2310mpwep.kicad_mod Publish 0.1.0 · Ray 2d ago
cdcvf2310mpwep.kicad_sym Publish 0.1.0 · Ray 2d ago
cdcvf2310mpwep.lbr Publish 0.1.0 · Ray 2d ago
cdcvf2310mpwep.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Initial commit: component/cdcvf2310mpwep · Ray 2d ago

CDCVF2310MPWEP

Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-24

CDCVF2310MPWEP from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground pin; the device has five GND pins (1, 6, 7, 18, 19).
2 VDD power_in DC power supply pin; the supply range is 2.3 V to 3.6 V.
3 1Y0 output Buffered clock output of group 1; it follows CLK when 1G is high and is held low when 1G is low.
4 1Y1 output Buffered clock output of group 1; it follows CLK when 1G is high and is held low when 1G is low.
5 1Y2 output Buffered clock output of group 1; it follows CLK when 1G is high and is held low when 1G is low.
6 GND power_in Ground pin; one of the five GND pins (1, 6, 7, 18, 19).
7 GND power_in Ground pin; one of the five GND pins (1, 6, 7, 18, 19).
8 1Y3 output Buffered clock output of group 1; it follows CLK when 1G is high and is held low when 1G is low.
9 1Y4 output Buffered clock output of group 1; it follows CLK when 1G is high and is held low when 1G is low.
10 VDD power_in DC power supply pin; the supply range is 2.3 V to 3.6 V.
11 1G input Active-high output enable for 1Y[0:4]; the outputs follow CLK while this pin is high, and changes take effect on the next CLK falling edge per the enable/disable timing.
12 2Y4 output Buffered clock output of group 2; it follows CLK when 2G is high and is held low when 2G is low.
13 2G input Active-high output enable for 2Y[0:4]; the outputs follow CLK while this pin is high, and changes take effect on the next CLK falling edge per the enable/disable timing.
14 VDD power_in DC power supply pin; the supply range is 2.3 V to 3.6 V.
15 VDD power_in DC power supply pin; the supply range is 2.3 V to 3.6 V.
16 2Y3 output Buffered clock output of group 2; it follows CLK when 2G is high and is held low when 2G is low.
17 2Y2 output Buffered clock output of group 2; it follows CLK when 2G is high and is held low when 2G is low.
18 GND power_in Ground pin; one of the five GND pins (1, 6, 7, 18, 19).
19 GND power_in Ground pin; one of the five GND pins (1, 6, 7, 18, 19).
20 2Y1 output Buffered clock output of group 2; it follows CLK when 2G is high and is held low when 2G is low.
21 2Y0 output Buffered clock output of group 2; it follows CLK when 2G is high and is held low when 2G is low.
22 VDD power_in DC power supply pin; the supply range is 2.3 V to 3.6 V.
23 VDD power_in DC power supply pin; the supply range is 2.3 V to 3.6 V.
24 CLK input Input reference clock; the clock frequency is specified up to 200 MHz at VDD = 3 V to 3.6 V and up to 170 MHz at VDD = 2.3 V to 2.7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Clock/Timing
Pins 24

CAD (KiCad official)

  • Symbol: CDCVF2310MPWEP
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cdcvf2310mpwep-etched.step / cdcvf2310mpwep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcvf2310mpwep.step / cdcvf2310mpwep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 a293ccc324fb9cf1, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF