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CDCS503TPWRQ1
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Texas Instruments Clock Buffers, Drivers, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CDCS503TPWRQ1
Texas Instruments · Clock Buffers, Drivers · TSSOP-8
CDCS503TPWRQ1 from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | LVCMOS clock input accepting a 3.3-V LVCMOS signal; input frequency is 8 to 32 MHz with FS = 0 and 8 to 27 MHz with FS = 1, and VIL is at most 0.3 VDD while VIH is at least 0.7 VDD. |
| 2 | SSC_SEL 0 | input | Spread-spectrum selection pin with internal pullup that, together with SSC_SEL 1, selects 0%, ±0.5%, ±1% or ±2% center spread. |
| 3 | SSC_SEL 1 | input | Spread-spectrum selection pin with internal pullup that, together with SSC_SEL 0, selects 0%, ±0.5%, ±1% or ±2% center spread. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | FS | input | Frequency multiplication selection pin with internal pullup; FS = 0 gives x1 output (fOUT 8 to 32 MHz) and FS = 1 gives x4 output (fOUT 32 to 108 MHz). |
| 6 | OUT | output | LVCMOS clock output that drives 15 pF test load with IOH/IOL of ±12 mA and goes to high-impedance when OE is low. |
| 7 | OE | input | Output enable pin with internal pullup; driving it low places OUT in the high-impedance (tri-state) condition. |
| 8 | VDD | power_in | 3.3-V power supply, operating range 3.0 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | RTC/Clock Chip |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
CDCS503TPWRQ1 - Footprint:
Package_SO:TSSOP-8_3x3mm_P0.65mm - 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files:
cdcs503tpwrq1-etched.step/cdcs503tpwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdcs503tpwrq1.step/cdcs503tpwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (16 pp, sha256
6e3887bd0be5c41d, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CDCS503TPWRQ1
**Texas Instruments** · Clock Buffers, Drivers · TSSOP-8
CDCS503TPWRQ1 from Texas Instruments, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | input | LVCMOS clock input accepting a 3.3-V LVCMOS signal; input frequency is 8 to 32 MHz with FS = 0 and 8 to 27 MHz with FS = 1, and VIL is at most 0.3 VDD while VIH is at least 0.7 VDD. |
| 2 | SSC_SEL 0 | input | Spread-spectrum selection pin with internal pullup that, together with SSC_SEL 1, selects 0%, ±0.5%, ±1% or ±2% center spread. |
| 3 | SSC_SEL 1 | input | Spread-spectrum selection pin with internal pullup that, together with SSC_SEL 0, selects 0%, ±0.5%, ±1% or ±2% center spread. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | FS | input | Frequency multiplication selection pin with internal pullup; FS = 0 gives x1 output (fOUT 8 to 32 MHz) and FS = 1 gives x4 output (fOUT 32 to 108 MHz). |
| 6 | OUT | output | LVCMOS clock output that drives 15 pF test load with IOH/IOL of ±12 mA and goes to high-impedance when OE is low. |
| 7 | OE | input | Output enable pin with internal pullup; driving it low places OUT in the high-impedance (tri-state) condition. |
| 8 | VDD | power_in | 3.3-V power supply, operating range 3.0 V to 3.6 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-8 |
| Category | RTC/Clock Chip |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `CDCS503TPWRQ1`
- Footprint: `Package_SO:TSSOP-8_3x3mm_P0.65mm`
- 3D model: TSSOP-8 (KiCad packages3D, STEP)
- 3D model files: `cdcs503tpwrq1-etched.step` / `cdcs503tpwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcs503tpwrq1.step` / `cdcs503tpwrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdcs503-q1) (16 pp, sha256 `6e3887bd0be5c41d`, retrieved 2026-10-07, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cdcs503tpwrq1-datasheet.pdf)