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CDCM6208V2RGZT

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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CDCM6208V2RGZT

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-48-EP(7x7)

CDCM6208V2RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SI_MODE0 input Serial interface / pin mode select bit 0 (LVCMOS input with 50-kΩ pulldown), decoded with SI_MODE1 as 00 SPI, 01 I2C, 10 Pin mode, 11 reserved.
2 SDI/SDA/PIN1 bidirectional SPI serial data input, I2C serial data (open-drain, requires a pullup resistor in I2C mode), or control pin 1 in pin mode.
3 SDO/AD0/PIN2 bidirectional SPI serial data output, I2C address offset bit 0 input, or control pin 2 in pin mode.
4 SCS/AD1/PIN3 input SPI latch enable, I2C address offset bit 1 input, or control pin 3 in pin mode (LVCMOS, no pull resistor).
5 SCL/PIN4 input SPI/I2C clock input or control pin 4 in pin mode (LVCMOS, no pull resistor).
6 REF_SEL input Manual reference selection MUX control (LVCMOS with 50-kΩ pullup): low (≤ VIL) selects PRI_REF, high (≥ VIH) selects SEC_REF when Register 4 bit 12 = 1.
7 VDD_PRI_REF power_in Analog supply for the primary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_SEC_REF.
8 PRI_REFP input Universal primary reference input, positive side of the differential pair.
9 PRI_REFN input Universal primary reference input, negative side of the differential pair.
10 VDD_SEC_REF power_in Analog supply for the secondary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_PRI_REF; it may be connected to GND if the secondary input buffer is disabled (Register 4 bit 5 = 0).
11 SEC_REFP input Universal secondary reference input, positive side of the differential pair.
12 SEC_REFN input Universal secondary reference input, negative side of the differential pair.
13 VDD_Y0_Y1 power_in Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of two pins).
14 Y0_P output Universal output 0, positive pin.
15 Y0_N output Universal output 0, negative pin.
16 Y1_N output Universal output 1, negative pin.
17 Y1_P output Universal output 1, positive pin.
18 VDD_Y0_Y1 power_in Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of two pins).
19 VDD_Y2_Y3 power_in Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of two pins).
20 Y2_P output Universal output 2, positive pin.
21 Y2_N output Universal output 2, negative pin.
22 Y3_N output Universal output 3, negative pin.
23 Y3_P output Universal output 3, positive pin.
24 VDD_Y2_Y3 power_in Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of two pins).
25 Y4_N output Universal output 4, negative pin.
26 Y4_P output Universal output 4, positive pin.
27 VDD_Y4 power_in Analog supply for output 4, set to 1.8 V, 2.5 V or 3.3 V.
28 Y5_N output Universal output 5, negative pin.
29 Y5_P output Universal output 5, positive pin.
30 VDD_Y5 power_in Analog supply for output 5, set to 1.8 V, 2.5 V or 3.3 V.
31 VDD_Y6 power_in Analog supply for output 6, set to 1.8 V, 2.5 V or 3.3 V.
32 Y6_P output Universal output 6, positive pin.
33 Y6_N output Universal output 6, negative pin.
34 VDD_Y7 power_in Analog supply for output 7, set to 1.8 V, 2.5 V or 3.3 V.
35 Y7_P output Universal output 7, positive pin.
36 Y7_N output Universal output 7, negative pin.
37 VDD_PLL1 power_in Analog power supply connection for PLL1 (on-chip LDO-regulated analog supply).
38 VDD_PLL2 power_in Analog power supply for the PLL; power-noise sensitive, may be combined with VDD_VCO.
39 VDD_VCO power_in Analog power supply for the PLL/VCO; power-noise sensitive, may be combined with VDD_PLL2.
40 REG_CAP output Analog regulator capacitor pin; connect a 10-µF capacitor with ESR below 1 Ω to GND at frequencies above 100 kHz.
41 ELF output Analog external loop filter pin for the PLL.
42 SYNCN input Active-low output synchronization input: outputs synchronize on a low-to-high transition, and holding it low disables all outputs (LVCMOS with 50-kΩ pullup).
43 PDN input Active-low power-down input (LVCMOS with 50-kΩ pullup): low disables the device and minimizes current, and exiting power-down resets the device and defaults all registers.
44 RESETN/PWR input In SPI/I2C mode an active-low reset (low = reset with registers retained); in pin mode it selects the core and I/O supply, 0 = 1.8 V and 1 = 2.5/3.3 V, and supplies must not be mixed.
45 STATUS1/PIN0 bidirectional LVCMOS status output 1 in SPI/I2C modes (no pull resistor), or control pin 0 in pin mode.
46 STATUS0 output LVCMOS status output 0, configurable to report reference selection, loss of reference or PLL unlock.
47 SI_MODE1 input Serial interface / pin mode select bit 1 (LVCMOS with 50-kΩ pullup), decoded with SI_MODE0 as 00 SPI, 01 I2C, 10 Pin mode, 11 reserved.
48 DVDD power_in Digital core supply and reference supply for all control inputs; must match the expected input signal swing of the control inputs.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Clock/Timing
Pins 49

CAD (KiCad official)

  • Symbol: CDCM6208V2RGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: cdcm6208v2rgzt-etched.step / cdcm6208v2rgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcm6208v2rgzt.step / cdcm6208v2rgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (94 pp, sha256 116fe17a57d62582, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF