component
CDCM6208V2RGZT
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+86@@ -0,0 +1,86 @@+# CDCM6208V2RGZT++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · VQFN-48-EP(7x7)++CDCM6208V2RGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SI_MODE0 | input | Serial interface / pin mode select bit 0 (LVCMOS input with 50-kΩ pulldown), decoded with SI_MODE1 as 00 SPI, 01 I2C, 10 Pin mode, 11 reserved. |+| 2 | SDI/SDA/PIN1 | bidirectional | SPI serial data input, I2C serial data (open-drain, requires a pullup resistor in I2C mode), or control pin 1 in pin mode. |+| 3 | SDO/AD0/PIN2 | bidirectional | SPI serial data output, I2C address offset bit 0 input, or control pin 2 in pin mode. |+| 4 | SCS/AD1/PIN3 | input | SPI latch enable, I2C address offset bit 1 input, or control pin 3 in pin mode (LVCMOS, no pull resistor). |+| 5 | SCL/PIN4 | input | SPI/I2C clock input or control pin 4 in pin mode (LVCMOS, no pull resistor). |+| 6 | REF_SEL | input | Manual reference selection MUX control (LVCMOS with 50-kΩ pullup): low (≤ VIL) selects PRI_REF, high (≥ VIH) selects SEC_REF when Register 4 bit 12 = 1. |+| 7 | VDD_PRI_REF | power_in | Analog supply for the primary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_SEC_REF. |+| 8 | PRI_REFP | input | Universal primary reference input, positive side of the differential pair. |+| 9 | PRI_REFN | input | Universal primary reference input, negative side of the differential pair. |+| 10 | VDD_SEC_REF | power_in | Analog supply for the secondary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_PRI_REF; it may be connected to GND if the secondary input buffer is disabled (Register 4 bit 5 = 0). |+| 11 | SEC_REFP | input | Universal secondary reference input, positive side of the differential pair. |+| 12 | SEC_REFN | input | Universal secondary reference input, negative side of the differential pair. |+| 13 | VDD_Y0_Y1 | power_in | Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of two pins). |+| 14 | Y0_P | output | Universal output 0, positive pin. |+| 15 | Y0_N | output | Universal output 0, negative pin. |+| 16 | Y1_N | output | Universal output 1, negative pin. |+| 17 | Y1_P | output | Universal output 1, positive pin. |+| 18 | VDD_Y0_Y1 | power_in | Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of two pins). |+| 19 | VDD_Y2_Y3 | power_in | Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of two pins). |+| 20 | Y2_P | output | Universal output 2, positive pin. |+| 21 | Y2_N | output | Universal output 2, negative pin. |+| 22 | Y3_N | output | Universal output 3, negative pin. |+| 23 | Y3_P | output | Universal output 3, positive pin. |+| 24 | VDD_Y2_Y3 | power_in | Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of two pins). |+| 25 | Y4_N | output | Universal output 4, negative pin. |+| 26 | Y4_P | output | Universal output 4, positive pin. |+| 27 | VDD_Y4 | power_in | Analog supply for output 4, set to 1.8 V, 2.5 V or 3.3 V. |+| 28 | Y5_N | output | Universal output 5, negative pin. |+| 29 | Y5_P | output | Universal output 5, positive pin. |+| 30 | VDD_Y5 | power_in | Analog supply for output 5, set to 1.8 V, 2.5 V or 3.3 V. |+| 31 | VDD_Y6 | power_in | Analog supply for output 6, set to 1.8 V, 2.5 V or 3.3 V. |+| 32 | Y6_P | output | Universal output 6, positive pin. |+| 33 | Y6_N | output | Universal output 6, negative pin. |+| 34 | VDD_Y7 | power_in | Analog supply for output 7, set to 1.8 V, 2.5 V or 3.3 V. |+| 35 | Y7_P | output | Universal output 7, positive pin. |+| 36 | Y7_N | output | Universal output 7, negative pin. |+| 37 | VDD_PLL1 | power_in | Analog power supply connection for PLL1 (on-chip LDO-regulated analog supply). |+| 38 | VDD_PLL2 | power_in | Analog power supply for the PLL; power-noise sensitive, may be combined with VDD_VCO. |+| 39 | VDD_VCO | power_in | Analog power supply for the PLL/VCO; power-noise sensitive, may be combined with VDD_PLL2. |+| 40 | REG_CAP | output | Analog regulator capacitor pin; connect a 10-µF capacitor with ESR below 1 Ω to GND at frequencies above 100 kHz. |+| 41 | ELF | output | Analog external loop filter pin for the PLL. |+| 42 | SYNCN | input | Active-low output synchronization input: outputs synchronize on a low-to-high transition, and holding it low disables all outputs (LVCMOS with 50-kΩ pullup). |+| 43 | PDN | input | Active-low power-down input (LVCMOS with 50-kΩ pullup): low disables the device and minimizes current, and exiting power-down resets the device and defaults all registers. |+| 44 | RESETN/PWR | input | In SPI/I2C mode an active-low reset (low = reset with registers retained); in pin mode it selects the core and I/O supply, 0 = 1.8 V and 1 = 2.5/3.3 V, and supplies must not be mixed. |+| 45 | STATUS1/PIN0 | bidirectional | LVCMOS status output 1 in SPI/I2C modes (no pull resistor), or control pin 0 in pin mode. |+| 46 | STATUS0 | output | LVCMOS status output 0, configurable to report reference selection, loss of reference or PLL unlock. |+| 47 | SI_MODE1 | input | Serial interface / pin mode select bit 1 (LVCMOS with 50-kΩ pullup), decoded with SI_MODE0 as 00 SPI, 01 I2C, 10 Pin mode, 11 reserved. |+| 48 | DVDD | power_in | Digital core supply and reference supply for all control inputs; must match the expected input signal swing of the control inputs. |+| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-48-EP(7x7) |+| Category | Clock/Timing |+| Pins | 49 |++## CAD (KiCad official)++- Symbol: `CDCM6208V2RGZT`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)+- 3D model files: `cdcm6208v2rgzt-etched.step` / `cdcm6208v2rgzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcm6208v2rgzt.step` / `cdcm6208v2rgzt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdcm6208) (94 pp, sha256 `116fe17a57d62582`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcm6208v2rgzt-datasheet.pdf)
page.jsonadded+447@@ -0,0 +1,447 @@+{+ "slug": "cdcm6208v2rgzt",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdcm6208v2rgzt",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdcm6208v2rgzt.kicad_sym",+ "cdcm6208v2rgzt.kicad_mod",+ "cdcm6208v2rgzt.glb",+ "cdcm6208v2rgzt.step",+ "cdcm6208v2rgzt.lbr",+ "docs/hero.png",+ "docs/cdcm6208v2rgzt-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cdcm6208v2rgzt-hero.glb",+ "cdcm6208v2rgzt-hero.overlay.json"+ ],+ "component": {+ "mpn": "CDCM6208V2RGZT",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-48-EP(7x7)",+ "pin_count": 49,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cdcm6208",+ "parts": {+ "symbol": "cdcm6208v2rgzt.kicad_sym",+ "footprint": "cdcm6208v2rgzt.kicad_mod",+ "model_3d": "cdcm6208v2rgzt-hero.glb",+ "model_3d_plain": "cdcm6208v2rgzt.glb",+ "model_3d_step": "cdcm6208v2rgzt-etched.step",+ "model_3d_step_plain": "cdcm6208v2rgzt.step",+ "lbr": "cdcm6208v2rgzt.lbr"+ },+ "distributor_links": {+ "lcsc": "C1519871",+ "digikey": "296-30502-2-ND",+ "mouser": "595-CDCM6208V2RGZT"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:26:25Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-30502-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CDCM6208V2RGZT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SI_MODE0",+ "type": "input",+ "description": "Serial interface / pin mode select bit 0 (LVCMOS input with 50-kΩ pulldown), decoded with SI_MODE1 as 00 SPI, 01 I2C, 10 Pin mode, 11 reserved."+ },+ {+ "number": "2",+ "name": "SDI/SDA/PIN1",+ "type": "bidirectional",+ "description": "SPI serial data input, I2C serial data (open-drain, requires a pullup resistor in I2C mode), or control pin 1 in pin mode."+ },+ {+ "number": "3",+ "name": "SDO/AD0/PIN2",+ "type": "bidirectional",+ "description": "SPI serial data output, I2C address offset bit 0 input, or control pin 2 in pin mode."+ },+ {+ "number": "4",+ "name": "SCS/AD1/PIN3",+ "type": "input",+ "description": "SPI latch enable, I2C address offset bit 1 input, or control pin 3 in pin mode (LVCMOS, no pull resistor)."+ },+ {+ "number": "5",+ "name": "SCL/PIN4",+ "type": "input",+ "description": "SPI/I2C clock input or control pin 4 in pin mode (LVCMOS, no pull resistor)."+ },+ {+ "number": "6",+ "name": "REF_SEL",+ "type": "input",+ "description": "Manual reference selection MUX control (LVCMOS with 50-kΩ pullup): low (≤ VIL) selects PRI_REF, high (≥ VIH) selects SEC_REF when Register 4 bit 12 = 1."+ },+ {+ "number": "7",+ "name": "VDD_PRI_REF",+ "type": "power_in",+ "description": "Analog supply for the primary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_SEC_REF."+ },+ {+ "number": "8",+ "name": "PRI_REFP",+ "type": "input",+ "description": "Universal primary reference input, positive side of the differential pair."+ },+ {+ "number": "9",+ "name": "PRI_REFN",+ "type": "input",+ "description": "Universal primary reference input, negative side of the differential pair."+ },+ {+ "number": "10",+ "name": "VDD_SEC_REF",+ "type": "power_in",+ "description": "Analog supply for the secondary reference inputs, set to 1.8 V, 2.5 V or 3.3 V, or connected to VDD_PRI_REF; it may be connected to GND if the secondary input buffer is disabled (Register 4 bit 5 = 0)."+ },+ {+ "number": "11",+ "name": "SEC_REFP",+ "type": "input",+ "description": "Universal secondary reference input, positive side of the differential pair."+ },+ {+ "number": "12",+ "name": "SEC_REFN",+ "type": "input",+ "description": "Universal secondary reference input, negative side of the differential pair."+ },+ {+ "number": "13",+ "name": "VDD_Y0_Y1",+ "type": "power_in",+ "description": "Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of two pins)."+ },+ {+ "number": "14",+ "name": "Y0_P",+ "type": "output",+ "description": "Universal output 0, positive pin."+ },+ {+ "number": "15",+ "name": "Y0_N",+ "type": "output",+ "description": "Universal output 0, negative pin."+ },+ {+ "number": "16",+ "name": "Y1_N",+ "type": "output",+ "description": "Universal output 1, negative pin."+ },+ {+ "number": "17",+ "name": "Y1_P",+ "type": "output",+ "description": "Universal output 1, positive pin."+ },+ {+ "number": "18",+ "name": "VDD_Y0_Y1",+ "type": "power_in",+ "description": "Analog supply for outputs 0 and 1, set to 1.8 V, 2.5 V or 3.3 V (one of two pins)."+ },+ {+ "number": "19",+ "name": "VDD_Y2_Y3",+ "type": "power_in",+ "description": "Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of two pins)."+ },+ {+ "number": "20",+ "name": "Y2_P",+ "type": "output",+ "description": "Universal output 2, positive pin."+ },+ {+ "number": "21",+ "name": "Y2_N",+ "type": "output",+ "description": "Universal output 2, negative pin."+ },+ {+ "number": "22",+ "name": "Y3_N",+ "type": "output",+ "description": "Universal output 3, negative pin."+ },+ {+ "number": "23",+ "name": "Y3_P",+ "type": "output",+ "description": "Universal output 3, positive pin."+ },+ {+ "number": "24",+ "name": "VDD_Y2_Y3",+ "type": "power_in",+ "description": "Analog supply for outputs 2 and 3, set to 1.8 V, 2.5 V or 3.3 V (one of two pins)."+ },+ {+ "number": "25",+ "name": "Y4_N",+ "type": "output",+ "description": "Universal output 4, negative pin."+ },+ {+ "number": "26",+ "name": "Y4_P",+ "type": "output",+ "description": "Universal output 4, positive pin."+ },+ {+ "number": "27",+ "name": "VDD_Y4",+ "type": "power_in",+ "description": "Analog supply for output 4, set to 1.8 V, 2.5 V or 3.3 V."+ },+ {+ "number": "28",+ "name": "Y5_N",+ "type": "output",+ "description": "Universal output 5, negative pin."+ },+ {+ "number": "29",+ "name": "Y5_P",+ "type": "output",+ "description": "Universal output 5, positive pin."+ },+ {+ "number": "30",+ "name": "VDD_Y5",+ "type": "power_in",+ "description": "Analog supply for output 5, set to 1.8 V, 2.5 V or 3.3 V."+ },+ {+ "number": "31",+ "name": "VDD_Y6",+ "type": "power_in",+ "description": "Analog supply for output 6, set to 1.8 V, 2.5 V or 3.3 V."+ },+ {+ "number": "32",+ "name": "Y6_P",+ "type": "output",+ "description": "Universal output 6, positive pin."+ },+ {+ "number": "33",+ "name": "Y6_N",+ "type": "output",+ "description": "Universal output 6, negative pin."+ },+ {+ "number": "34",+ "name": "VDD_Y7",+ "type": "power_in",+ "description": "Analog supply for output 7, set to 1.8 V, 2.5 V or 3.3 V."+ },+ {+ "number": "35",+ "name": "Y7_P",+ "type": "output",+ "description": "Universal output 7, positive pin."+ },+ {+ "number": "36",+ "name": "Y7_N",+ "type": "output",+ "description": "Universal output 7, negative pin."+ },+ {+ "number": "37",+ "name": "VDD_PLL1",+ "type": "power_in",+ "description": "Analog power supply connection for PLL1 (on-chip LDO-regulated analog supply)."+ },+ {+ "number": "38",+ "name": "VDD_PLL2",+ "type": "power_in",+ "description": "Analog power supply for the PLL; power-noise sensitive, may be combined with VDD_VCO."+ },+ {+ "number": "39",+ "name": "VDD_VCO",+ "type": "power_in",+ "description": "Analog power supply for the PLL/VCO; power-noise sensitive, may be combined with VDD_PLL2."+ },+ {+ "number": "40",+ "name": "REG_CAP",+ "type": "output",+ "description": "Analog regulator capacitor pin; connect a 10-µF capacitor with ESR below 1 Ω to GND at frequencies above 100 kHz."+ },+ {+ "number": "41",+ "name": "ELF",+ "type": "output",+ "description": "Analog external loop filter pin for the PLL."+ },+ {+ "number": "42",+ "name": "SYNCN",+ "type": "input",+ "description": "Active-low output synchronization input: outputs synchronize on a low-to-high transition, and holding it low disables all outputs (LVCMOS with 50-kΩ pullup)."+ },+ {+ "number": "43",+ "name": "PDN",+ "type": "input",+ "description": "Active-low power-down input (LVCMOS with 50-kΩ pullup): low disables the device and minimizes current, and exiting power-down resets the device and defaults all registers."+ },+ {+ "number": "44",+ "name": "RESETN/PWR",+ "type": "input",+ "description": "In SPI/I2C mode an active-low reset (low = reset with registers retained); in pin mode it selects the core and I/O supply, 0 = 1.8 V and 1 = 2.5/3.3 V, and supplies must not be mixed."+ },+ {+ "number": "45",+ "name": "STATUS1/PIN0",+ "type": "bidirectional",+ "description": "LVCMOS status output 1 in SPI/I2C modes (no pull resistor), or control pin 0 in pin mode."+ },+ {+ "number": "46",+ "name": "STATUS0",+ "type": "output",+ "description": "LVCMOS status output 0, configurable to report reference selection, loss of reference or PLL unlock."+ },+ {+ "number": "47",+ "name": "SI_MODE1",+ "type": "input",+ "description": "Serial interface / pin mode select bit 1 (LVCMOS with 50-kΩ pullup), decoded with SI_MODE0 as 00 SPI, 01 I2C, 10 Pin mode, 11 reserved."+ },+ {+ "number": "48",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital core supply and reference supply for all control inputs; must match the expected input signal swing of the control inputs."+ },+ {+ "number": "49",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet lists a 'GND PAD' (Power Supply Ground and Thermal Pad) for the VQFN package but does ; The top-view pin diagram text on page 4 is garbled in the extracted text. Pin numbers were taken fro; Pin names VDD_Y0_Y1 (13, 18), VDD_Y2_Y3 (19, 24) are shared between two physical pins in the datashe",+ "exposed pad 49 added from the footprint"+ ],+ "pages_sent": 20,+ "cost_usd": 0.1596,+ "at": "2026-10-07T21:26:06"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cdcm6208",+ "pages": 94,+ "sha256": "116fe17a57d62582",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 49,+ "described": 49,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdcm6208v2rgzt.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdcm6208v2rgzt-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 7,+ 7,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e310966a8fb514bb9cf820f1de5c089b4b5d194cd5cfe9e6e35b3c860f70bc05",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}