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CDCM61001RHBR

Public Made by Adom

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Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timingcdcm61001rhbrfactory-2.0.0extractor-text

Verified CDCM61001RHBR

by Ray · last 10 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

10 Nov 2026RayPublished by the parts factory: tier mfr, 33 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCM61001RHBR · VQFN-32-EP(5x5) · 33 pins
  • ✓copper: 33 copper pads, none touching another net
  • ✓datasheet: all 33 pin names found in the 36-page datasheet
  • ✓distributor: lcsc C2861473, digikey 296-48510-2-ND, mouser 595-CDCM61001RHBR
  • ✓family: QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-say5zy5c/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.33)
  • ✓pads: 33 pins = 33 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 33 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 39 kB, viewers/symbol.html 23 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdcm61001rhbr.kicad_sym✓ cdcm61001rhbr.kicad_mod✓ cdcm61001rhbr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cdcm61001rhbr: viewers rendered from the public page · Ray
cdcm61001rhbr-etched.glb Publish 0.1.0 · Ray
cdcm61001rhbr-etched.step cdcm61001rhbr: factory component page (tier=mfr) · Ray
cdcm61001rhbr-hero.glb cdcm61001rhbr: hero GLB from the etched model (keeps the MPN mark) · Ray
cdcm61001rhbr-hero.overlay.json Publish 0.1.0 · Ray
cdcm61001rhbr.glb Publish 0.1.0 · Ray
cdcm61001rhbr.kicad_mod Publish 0.1.0 · Ray
cdcm61001rhbr.kicad_sym Publish 0.1.0 · Ray
cdcm61001rhbr.lbr Publish 0.1.0 · Ray
cdcm61001rhbr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 33 pins · Ray

CDCM61001RHBR

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-32-EP(5x5)

CDCM61001RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connection (NC) per the datasheet pin function table.
2 NC unconnected No connection (NC) per the datasheet pin function table.
3 NC unconnected No connection (NC) per the datasheet pin function table.
4 VCC_OUT power_in 3.3-V supply for the output buffer, with a recommended operating range of 3.0 V to 3.6 V.
5 OUTN output Differential output pair (complement) or one of two single-ended outputs, with type set by OS1/OS0 (LVPECL, LVDS, or LVCMOS).
6 OUTP output Differential output pair (true) or one of two single-ended outputs, with type set by OS1/OS0 (LVPECL, LVDS, or LVCMOS).
7 CE input Chip enable with an internal 150-kΩ pull-up: CE low powers down the device with outputs Hi-Z, and CE high gives normal active operation.
8 NC unconnected No connection (NC) per the datasheet pin function table.
9 VCC_VCO power_in 3.3-V supply for the internal VCO, with a recommended operating range of 3.0 V to 3.6 V.
10 OS1 input Output type select control pin (with OS0, per Table 6) with an internal pull-up.
11 OS0 input Output type select control pin (with OS1, per Table 6) with an internal pull-up.
12 RSTN input Device reset, active low, with an internal pull-up; a low level resets the device with outputs Hi-Z, and a 0-to-1 transition starts PLL recalibration.
13 OD0 input Output divider control pin (with OD1 and OD2, per Table 5) with an internal pull-up; code 100 and 110 are reserved.
14 OD1 input Output divider control pin (with OD0 and OD2, per Table 5) with an internal pull-up; code 100 and 110 are reserved.
15 OD2 input Output divider control pin (with OD0 and OD1, per Table 5) with an internal pull-up; selects divide ratios 1 to 8.
16 VCC_PLL2 power_in 3.3-V supply for the PLL circuitry, with a recommended operating range of 3.0 V to 3.6 V.
17 REG_CAP2 output Capacitor connection for the internal regulator, which must be connected to GND with a 10-μF Y5V capacitor.
18 VCC_PLL1 power_in 3.3-V supply for the PLL circuitry, with a recommended operating range of 3.0 V to 3.6 V.
19 REG_CAP1 output Capacitor connection for the internal regulator, which must be connected to GND with a 10-μF Y5V capacitor.
20 VCC_IN power_in 3.3-V supply for the input buffers, with a recommended operating range of 3.0 V to 3.6 V.
21 XIN input Parallel resonant crystal connection (other crystal pad to GND) or LVCMOS reference input, with input frequency range 21.875 MHz to 28.47 MHz.
22 GND1 power_in Additional ground pin, shorted on-chip to GND.
23 OSC_OUT output Bypass LVCMOS output used to monitor crystal loading, which turns on at power-up and is present during VCO calibration.
24 NC unconnected No connection (NC) per the datasheet pin function table.
25 PR0 input Prescaler and feedback divider control pin (with PR1, per Table 4) with an internal pull-up.
26 PR1 input Prescaler and feedback divider control pin (with PR0, per Table 4) with an internal pull-up.
27 NC unconnected No connection (NC) per the datasheet pin function table.
28 NC unconnected No connection (NC) per the datasheet pin function table.
29 NC unconnected No connection (NC) per the datasheet pin function table.
30 NC unconnected No connection (NC) per the datasheet pin function table.
31 NC unconnected No connection (NC) per the datasheet pin function table.
32 NC unconnected No connection (NC) per the datasheet pin function table.
33 GND power_in Exposed thermal pad that is the ground connection and must be soldered to the PCB ground for heat removal and electrical grounding.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(5x5)
Category Clock/Timing
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input low current IIL -200 μA VCC = 3 V, VIH = 3.6 V 4
Input high current IIH 200 μA VCC = 3.6 V, VIL = 0 V 4
Supply voltage range VCC_OUT, VCC_PLL1, VCC_PLL2, VCC_VCO, VCC_IN -0.5 4.6 V 3
Input voltage range VIN -0.5 V 3
Output voltage range VOUT -0.5 V 3
Input current IIN 20 mA 3
Output current IOUT 50 mA 3
Storage temperature range TSTG -65 150 °C 3
Output supply voltage VCC_OUT 3 3.3 3.6 V 3
PLL supply voltage VCC_PLL1 3 3.3 3.6 V 3
On-chip VCO supply voltage VCC_VCO 3 3.3 3.6 V 3
Input supply voltage VCC_IN 3 3.3 3.6 V 3
Ambient temperature TA -40 85 °C 3
Bypass output frequency fOSC_OUT 21.875 28.47 MHz 4
Output frequency fOUT 43.75 250 MHz 4
Output low voltage VOL 0.3 V VCC = min to max, IOL = 100 μA 4
RMS phase jitter tRJIT 0.85 ps RMS 250 MHz (10 kHz to 20 MHz) 4
Output rise/fall slew rate tSLEW-RATE 2.4 V/ns 20% to 80% 4
Output duty cycle ODC 45 55 % 4
Device current, LVCMOS ICC 95 110 mA fIN = 25 MHz, fOUT = 250 MHz, CL = 5 pF 4
Output frequency fOUT 43.75 683.264 MHz 4
Differential output voltage /VOD/ 0.6 1.23 V 4
RMS phase jitter tRJIT 0.77 ps RMS 625 MHz (10 kHz to 20 MHz) 4
Output rise/fall time tR/tF 175 ps 20% to 80% 4
Device current, LVPECL ICC 100 115 mA fIN = 25 MHz, fOUT = 625 MHz 4
Differential output voltage /VOD/ 0.247 0.454 V 4
VDD magnitude change ΔVOD 50 mV 4
Common-mode voltage VOS 1.125 1.375 V 4
VOS magnitude change ΔVOS 50 mV 4
RMS phase jitter tRJIT 0.73 ps RMS 625 MHz (10 kHz to 20 MHz) 4
Output rise/fall time tR/tF 255 ps 20% to 80% 4
Device current, LVDS ICC 90 105 mA fIN = 25 MHz, fOUT = 625 MHz 4
Thermal resistance, junction-to-ambient θJA 35 °C/W 0 LFM 3
Thermal resistance, junction-to-pad θJP 4 °C/W 3

CAD (KiCad official)

  • Symbol: CDCM61001RHBR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: cdcm61001rhbr-etched.step / cdcm61001rhbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcm61001rhbr.step / cdcm61001rhbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 ee7411bbf510cdd5, retrieved 2026-11-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF