CDCM1802RGTR

{
  "slug": "cdcm1802rgtr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Clock Buffers, Drivers, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "rtc-clock chip",
    "cdcm1802rgtr",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cdcm1802rgtr.kicad_sym",
    "cdcm1802rgtr.kicad_mod",
    "cdcm1802rgtr.glb",
    "cdcm1802rgtr.step",
    "cdcm1802rgtr.lbr",
    "docs/hero.png",
    "docs/cdcm1802rgtr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cdcm1802rgtr-hero.glb",
    "cdcm1802rgtr-hero.overlay.json",
    "cdcm1802rgtr-etched.glb"
  ],
  "component": {
    "mpn": "CDCM1802RGTR",
    "manufacturer": "Texas Instruments",
    "package": "VQFN-16-EP(3x3)",
    "pin_count": 17,
    "category": "RTC/Clock Chip",
    "subcategory": "Clock Buffers, Drivers",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cdcm1802.pdf",
    "parts": {
      "symbol": "cdcm1802rgtr.kicad_sym",
      "footprint": "cdcm1802rgtr.kicad_mod",
      "model_3d": "cdcm1802rgtr-hero.glb",
      "model_3d_plain": "cdcm1802rgtr-etched.glb",
      "model_3d_step": "cdcm1802rgtr-etched.step",
      "model_3d_step_plain": "cdcm1802rgtr.step",
      "lbr": "cdcm1802rgtr.lbr"
    },
    "distributor_links": {
      "lcsc": "C701742",
      "digikey": "CDCM1802RGTR-ND",
      "mouser": "595-CDCM1802RGTR"
    },
    "distributor_check": {
      "checked_at": "2026-11-02T16:40:42Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "CDCM1802RGTR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "595-CDCM1802RGTR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "VDDPECL",
        "type": "power_in",
        "description": "Supply voltage for the PECL input and internal logic, which should have the same value as VDD0 and VDD1."
      },
      {
        "number": "2",
        "name": "IN",
        "type": "input",
        "description": "Differential clock input with a wide common-mode range; the input is high-impedance and must not be reverse-biased, so the input voltage must stay below VDD."
      },
      {
        "number": "3",
        "name": "IN",
        "type": "input",
        "description": "Complementary differential clock input, which can be tied to a DC reference such as VCC/2 for single-ended operation."
      },
      {
        "number": "4",
        "name": "VBB",
        "type": "output",
        "description": "Output bias voltage at VDD − 1.3 V for biasing the unused complementary input, with output current drive limited to about 1.5 mA."
      },
      {
        "number": "5",
        "name": "VSS",
        "type": "power_in",
        "description": "Device ground."
      },
      {
        "number": "6",
        "name": "VSS",
        "type": "power_in",
        "description": "Device ground."
      },
      {
        "number": "7",
        "name": "Y1",
        "type": "output",
        "description": "LVCMOS clock output that provides a copy of or a divided copy of IN depending on the S0, S1 and EN mode, and can be disabled by tying VDD1 to GND."
      },
      {
        "number": "8",
        "name": "VDD1",
        "type": "power_in",
        "description": "Supply voltage for the CMOS output, which can be disabled by pulling it to GND and must not be driven from outside while in that mode."
      },
      {
        "number": "9",
        "name": "VDD0",
        "type": "power_in",
        "description": "PECL output supply voltage for output Y0, which can be disabled by pulling it to GND."
      },
      {
        "number": "10",
        "name": "Y0",
        "type": "output",
        "description": "LVPECL clock output that provides a copy of or a divided copy of IN depending on the S1, S0 and EN mode; it can be left open to save power if unused."
      },
      {
        "number": "11",
        "name": "Y0",
        "type": "output",
        "description": "Complementary LVPECL clock output that forms the differential pair with Y0 and can be left open if unused."
      },
      {
        "number": "12",
        "name": "VDD0",
        "type": "power_in",
        "description": "PECL output supply voltage for output Y0, which can be disabled by pulling it to GND."
      },
      {
        "number": "13",
        "name": "S0",
        "type": "input",
        "description": "Three-level mode select input that defines the output configuration of Y0 and Y1 when tied to GND, pulled through 60 kΩ to VDD/2, or left floating."
      },
      {
        "number": "14",
        "name": "VSS",
        "type": "power_in",
        "description": "Device ground."
      },
      {
        "number": "15",
        "name": "S1",
        "type": "input",
        "description": "Three-level mode select input (with 60-kΩ pullup) that defines the output configuration of Y0 and Y1 when tied to GND, pulled through 60 kΩ to VDD/2, or left floating."
      },
      {
        "number": "16",
        "name": "EN",
        "type": "input",
        "description": "Enable input (with 60-kΩ pullup) that turns all outputs on or off simultaneously; EN = 0 sets Y[1:0] to high-impedance."
      },
      {
        "number": "17",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pins 3 and 11 are the complementary differential outputs/inputs. The text prints both as 'IN' and 'Y"
        ],
        "pages_sent": 7,
        "cost_usd": 0.0204,
        "at": "2026-11-02T16:40:33"
      },
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cdcm1802.pdf",
        "pages": 31,
        "sha256": "05c0a3dd9bb1c33d",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "cdcm1802rgtr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.0,
          3.0,
          0.785
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cdcm1802rgtr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          3.0,
          3.0,
          0.785
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d798cc787f63c3c240a583646265e5f7c953d7aa04442b8cf9938f2ff4fbb972",
        "checked": "2026-11-02",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}