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CDCM1802RGTR

Public Made by Adom

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Texas Instruments Clock Buffers, Drivers, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcdcm1802rgtrfactory-2.0.0extractor-text

Verified CDCM1802RGTR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCM1802RGTR · VQFN-16-EP(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 31-page datasheet
  • ✓distributor: lcsc C701742, digikey CDCM1802RGTR-ND, mouser 595-CDCM1802RGTR
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-djmy3pkt/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdcm1802rgtr.kicad_sym✓ cdcm1802rgtr.kicad_mod✓ cdcm1802rgtr.step
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CDCM1802RGTR

Texas Instruments · Clock Buffers, Drivers · VQFN-16-EP(3x3)

CDCM1802RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDDPECL power_in Supply voltage for the PECL input and internal logic, which should have the same value as VDD0 and VDD1.
2 IN input Differential clock input with a wide common-mode range; the input is high-impedance and must not be reverse-biased, so the input voltage must stay below VDD.
3 IN input Complementary differential clock input, which can be tied to a DC reference such as VCC/2 for single-ended operation.
4 VBB output Output bias voltage at VDD − 1.3 V for biasing the unused complementary input, with output current drive limited to about 1.5 mA.
5 VSS power_in Device ground.
6 VSS power_in Device ground.
7 Y1 output LVCMOS clock output that provides a copy of or a divided copy of IN depending on the S0, S1 and EN mode, and can be disabled by tying VDD1 to GND.
8 VDD1 power_in Supply voltage for the CMOS output, which can be disabled by pulling it to GND and must not be driven from outside while in that mode.
9 VDD0 power_in PECL output supply voltage for output Y0, which can be disabled by pulling it to GND.
10 Y0 output LVPECL clock output that provides a copy of or a divided copy of IN depending on the S1, S0 and EN mode; it can be left open to save power if unused.
11 Y0 output Complementary LVPECL clock output that forms the differential pair with Y0 and can be left open if unused.
12 VDD0 power_in PECL output supply voltage for output Y0, which can be disabled by pulling it to GND.
13 S0 input Three-level mode select input that defines the output configuration of Y0 and Y1 when tied to GND, pulled through 60 kΩ to VDD/2, or left floating.
14 VSS power_in Device ground.
15 S1 input Three-level mode select input (with 60-kΩ pullup) that defines the output configuration of Y0 and Y1 when tied to GND, pulled through 60 kΩ to VDD/2, or left floating.
16 EN input Enable input (with 60-kΩ pullup) that turns all outputs on or off simultaneously; EN = 0 sets Y[1:0] to high-impedance.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category RTC/Clock Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.3 3.8 V 4
Maximum junction temperature TJ 125 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage VDD 3 3.3 3.6 V 4
Supply voltage (functionality only) VDD 2.375 3.6 V 4
Operating free-air temperature TA -40 85 °C 4
Junction-to-ambient thermal resistance RθJA 48.4 °C/W 4
Junction-to-case (top) thermal resistance RθJC(top) 66.9 °C/W 4
Junction-to-board thermal resistance RθJB 22.5 °C/W 4
Junction-to-top characterization parameter ψJT 1.7 °C/W 4
Junction-to-board characterization parameter ψJB 22.5 °C/W 4
Junction-to-case (bottom) thermal resistance RθJC(bot) 5.8 °C/W 4
Input frequency fclk 0 800 MHz LVPECL input 5
High-level input common mode VCM 1 V 5
Input voltage swing between IN and IN VIN 500 1300 mV See (1) 5
Input voltage swing between IN and IN VIN 150 1300 mV See (2) 5
Input current IIN -10 10 µA VI = VDD or 0 V 5
Input impedance RIN 300 kΩ 5
Input capacitance at IN, IN CI 1 pF 5
Output frequency fclk 0 800 MHz LVPECL output (see Figure 3) 5
Output voltage swing between Y and Y VO 500 mV Termination with 50 Ω to VDD − 2 V (see Figure 3) 5
Output 3-state current low IOZL 5 µA VDD = 3.6 V, VO = 0 V 5
Output 3-state current high IOZH 10 µA VDD = 3.6 V, VO = VDD, 0.8 V 5
Output frequency fclk 0 200 MHz LVCMOS output Y1 (see Figure 4) 5
High-level output voltage VOH 2.4 V VDD = 3 V, IOH = −6 mA 5
High-level output voltage VOH 2 V VDD = 3 V, IOH = −12 mA 5
Low-level output voltage VOL 0.5 V VDD = 3 V, IOL = 6 mA 5
Low-level output voltage VOL 0.8 V VDD = 3 V, IOL = 12 mA 5
Low-level output voltage VOL 0.1 V VDD = min to max, IOL = 100 µA 5
High-level output current IOH -29 mA VDD = 3.3 V, VO = 1.65 V 5
Low-level output current IOL 37 mA VDD = 3.3 V, VO = 1.65 V 5
High-impedance state output current IOZ -5 5 µA VDD = 3.6 V, VO = VDD or 0 V 5
Duty cycle distortion (LVPECL) tDuty -50 50 ps Crossing point-to-crossing point 6
Part-to-part skew (LVPECL) tsk(pp) 50 ps Any Y0 (see Note A in Figure 7) 6
Rise and fall time (LVPECL) tr/tf 200 350 ps 20% to 80% of VOUTPP (see Figure 8) 6
Propagation delay rising edge tpd(lh) 320 600 ps VOX to VOX 6
Propagation delay falling edge tpd(hl) 320 600 ps VOX to VOX 6
LVPECL pulse skew tsk(p) 100 ps VOX to VOX (see Note B in Figure 7) 6
Output skew between Y1 and Y0 tskLVCMOS(o) 1.6 ns VOX to VDD / 2 (see Figure 7) 6
Output duty cycle distortion (LVCMOS) tDuty -150 150 ps Measured at VDD / 2 6
Part-to-part skew Y1 tsk(pp) 300 ps Note A in Figure 7 6
Propagation delay rising edge from IN to Y1 tpd(lh) 1.6 2.6 ns VOX to VDD / 2 load (see Figure 9) 6
Propagation delay falling edge from IN to Y1 tpd(hl) 1.6 2.6 ns VOX to VDD / 2 load (see Figure 9) 6
Output rise slew rate tr 1.4 2.3 V/ns 20% to 80% of swing (see Figure 9) 6
Output fall slew rate tf 1.4 2.3 V/ns 80% to 20% of swing (see Figure 9) 6
Additive phase jitter from input to LVPECL output Y0 tjitterLVPECL 0.15 ps rms 12 kHz to 20 MHz, fout = 250 MHz to 800 MHz, divide by 1 mode 6
Additive phase jitter from input to LVPECL output Y0 tjitterLVPECL 0.25 ps rms 50 kHz to 40 MHz, fout = 250 MHz to 800 MHz, divide by 1 mode 6
Additive phase jitter from input to LVCMOS output Y1 tjitterLVCMOS 0.25 ps rms 12 kHz to 20 MHz, fout = 250 MHz, divide by 1 mode 6
Additive phase jitter from input to LVCMOS output Y1 tjitterLVCMOS 0.4 ps rms 50 kHz to 40 MHz, fout = 250 MHz, divide by 1 mode 6
Supply current, full load IDD 100 mA All outputs enabled, terminated, f = 800 MHz LVPECL and 200 MHz LVCMOS, VDD = 3.3 V 6
Supply current, no load IDD 85 mA Outputs enabled, no output load, f = 800 MHz LVPECL and 200 MHz LVCMOS, VDD = 3.6 V 6
Supply current, 3-state IDDZ 0.5 mA All outputs 3-state by control logic, f = 0 Hz, VDD = 3.6 V 6
Internal pullup resistor on S0, S1, and EN input Rpullup 42 60 78 kΩ 7
Input current, S0, S1, and EN pin IIL 38 85 µA VI = GND 7
Setup time, S0, S1, and EN pin before clock IN tsu 25 ns 7
Hold time, S0, S1, and EN pin after clock IN th 0 ns 7
Time between latching EN low transition and all outputs disabled t(disable) 10 ns 7
Time between latching EN low-to-high transition and outputs enabled t(enable) 1 µs 7

CAD (KiCad official)

  • Symbol: CDCM1802RGTR
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: cdcm1802rgtr-etched.step / cdcm1802rgtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdcm1802rgtr.step / cdcm1802rgtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 05c0a3dd9bb1c33d, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF