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CDCLVP2106RHAT

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Texas Instruments Clock Buffers, Drivers, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timingcdclvp2106rhatfactory-2.0.0extractor-text

Verified CDCLVP2106RHAT

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCLVP2106RHAT · VQFN-40-EP(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 34-page datasheet
  • ✓distributor: lcsc C2672996, digikey 296-25142-2-ND, mouser 595-CDCLVP2106RHAT
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-pl61a24m/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.31)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdclvp2106rhat.kicad_sym✓ cdclvp2106rhat.kicad_mod✓ cdclvp2106rhat.step
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CDCLVP2106RHAT

Texas Instruments · Clock Buffers, Drivers · VQFN-40-EP(6x6)

CDCLVP2106RHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No connect; do not connect.
2 INP1 input Positive side of differential input pair or single-ended input no. 1.
3 INN1 input Negative side of differential input pair or single-ended input no. 1.
4 VAC_REF1 power_out Bias voltage output for capacitive coupled input pair no. 1; do not use at VCC < 3 V, 0.1-µF capacitor to GND recommended, output current limited to 2 mA.
5 VCC power_in 2.5-V or 3.3-V supply for the device.
6 VCC power_in 2.5-V or 3.3-V supply for the device.
7 VAC_REF0 power_out Bias voltage output for capacitive coupled input pair no. 0; do not use at VCC < 3 V, 0.1-µF capacitor to GND recommended, output current limited to 2 mA.
8 INN0 input Negative side of differential input pair or single-ended input no. 0.
9 INP0 input Positive side of differential input pair or single-ended input no. 0.
10 NC unconnected No connect; do not connect.
11 VCC power_in 2.5-V or 3.3-V supply for the device.
12 OUTP0 output Positive side of differential LVPECL output pair no. 0.
13 OUTN0 output Negative side of differential LVPECL output pair no. 0.
14 OUTP1 output Positive side of differential LVPECL output pair no. 1.
15 OUTN1 output Negative side of differential LVPECL output pair no. 1.
16 OUTP2 output Positive side of differential LVPECL output pair no. 2.
17 OUTN2 output Negative side of differential LVPECL output pair no. 2.
18 OUTP3 output Positive side of differential LVPECL output pair no. 3.
19 OUTN3 output Negative side of differential LVPECL output pair no. 3.
20 VCC power_in 2.5-V or 3.3-V supply for the device.
21 GND1 power_in Device ground.
22 OUTP4 output Positive side of differential LVPECL output pair no. 4.
23 OUTN4 output Negative side of differential LVPECL output pair no. 4.
24 OUTP5 output Positive side of differential LVPECL output pair no. 5.
25 OUTN5 output Negative side of differential LVPECL output pair no. 5.
26 OUTP6 output Positive side of differential LVPECL output pair no. 6.
27 OUTN6 output Negative side of differential LVPECL output pair no. 6.
28 OUTP7 output Positive side of differential LVPECL output pair no. 7.
29 OUTN7 output Negative side of differential LVPECL output pair no. 7.
30 GND2 power_in Device ground.
31 VCC power_in 2.5-V or 3.3-V supply for the device.
32 OUTP8 output Positive side of differential LVPECL output pair no. 8.
33 OUTN8 output Negative side of differential LVPECL output pair no. 8.
34 OUTP9 output Positive side of differential LVPECL output pair no. 9.
35 OUTN9 output Negative side of differential LVPECL output pair no. 9.
36 OUTP10 output Positive side of differential LVPECL output pair no. 10.
37 OUTN10 output Negative side of differential LVPECL output pair no. 10.
38 OUTP11 output Positive side of differential LVPECL output pair no. 11.
39 OUTN11 output Negative side of differential LVPECL output pair no. 11.
40 VCC power_in 2.5-V or 3.3-V supply for the device.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Clock and Timing
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 4.6 V 6
Input voltage VIN -0.5 V 6
Output voltage VOUT -0.5 V 6
Input current IIN 20 mA 6
Output current IOUT 50 mA 6
Specified free-air temperature TA -40 85 °C no airflow 6
Maximum junction temperature TJ 125 °C 6
Storage temperature Tstg -65 150 °C 6
Supply voltage VCC 2.375 3.6 V 6
Ambient temperature TA -40 85 °C 6
PCB temperature (measured at thermal pad) TPCB 105 °C 6
Input frequency (LVCMOS input) fIN 200 MHz 7
Input threshold voltage Vth 1.1 1.8 V External threshold voltage applied to complementary input 7
Input low voltage VIL 0 V 7
Input high current IIH 40 μA VCC = 3.6 V, VIH = 3.6 V 7
Input low current IIL -40 μA VCC = 3.6 V, VIL = 0 V 7
Input edge rate ΔV/ΔT 1.5 V/ns 20% to 80% 7
Input capacitance (LVCMOS input) ICAP 5 pF 7
Input frequency (differential input) fIN 2000 MHz Clock input 7
Differential input peak-peak voltage VIN,DIFF,PP 0.1 1.5 V fIN ≤ 1.5 GHz 7
Differential input peak-peak voltage VIN,DIFF,PP 0.2 1.5 V 1.5 GHz ≤ fIN ≤ 2 GHz 7
Input high current (differential input) IIH 40 μA VCC = 3.6 V, VIH = 3.6 V 7
Input low current (differential input) IIL -40 μA VCC = 3.6 V, VIL = 0 V 7
Input edge rate (differential input) ΔV/ΔT 1.5 V/ns 20% to 80% 7
Input capacitance (differential input) ICAP 5 pF 7
Differential output peak-peak voltage (VCC 2.375-2.625 V) VOUT,DIFF,PP 0.5 1.35 V fIN ≤ 2 GHz 7
Supply internal current (VCC 2.375-2.625 V) IEE 92 mA Outputs unterminated, TA ≤ 85°C 7
Supply internal current (VCC 2.375-2.625 V) IEE 93 mA Outputs unterminated, TPCB ≤ 105°C 7
Output and internal supply current (VCC 2.375-2.625 V) ICC 477 mA All outputs terminated, 50 Ω to VCC, 2, TA ≤ 85°C 7
Output and internal supply current (VCC 2.375-2.625 V) ICC 526 mA All outputs terminated, 50 Ω to VCC, 2, TPCB ≤ 105°C 7
Differential output peak-peak voltage (VCC 3-3.6 V) VOUT,DIFF,PP 0.65 1.35 V fIN ≤ 2 GHz 8
Supply internal current (VCC 3-3.6 V) IEE 92 mA Outputs unterminated, TA ≤ 85°C 8
Supply internal current (VCC 3-3.6 V) IEE 93 mA Outputs unterminated, TPCB ≤ 105°C 8
Output and internal supply current (VCC 3-3.6 V) ICC 477 mA All outputs terminated, 50 Ω to VCC, 2, TA ≤ 85°C 8
Output and internal supply current (VCC 3-3.6 V) ICC 526 mA All outputs terminated, 50 Ω to VCC, 2, TPCB ≤ 105°C 8
Propagation delay tPD 550 ps VIN,DIFF,PP = 0.1 V 8
Part-to-part skew tSK,PP 150 ps 8
Within bank output skew tSK,O_WB 20 ps 8
Bank-to-bank output skew tSK,O_BB 25 ps Both inputs have equal skew 8
Pulse skew (crossing-point-to-crossing-point distortion) tSK,P -50 50 ps with 50% duty cycle input, fOUT = 100 MHz 8
Output rise/fall time tR/tF 200 ps 20% to 80% 9
Propagation delay (VCC 3-3.6 V) tPD 550 ps VIN,DIFF,PP = 0.1 V 9
Part-to-part skew (VCC 3-3.6 V) tSK,PP 150 ps 9
Within bank output skew (VCC 3-3.6 V) tSK,O_WB 20 ps 9
Bank-to-bank output skew (VCC 3-3.6 V) tSK,O_BB 25 ps Both inputs have equal skew 9
Pulse skew (VCC 3-3.6 V) tSK,P -50 50 ps with 50% duty cycle input, fOUT = 100 MHz 9
Junction-to-ambient thermal resistance RθJA 34.7 °C/W 0 LFM 6
Junction-to-case (top) thermal resistance RθJC(top) 23.7 °C/W 6
Junction-to-board thermal resistance RθJB 10.1 °C/W 6
Junction-to-top characterization parameter ψJT 0.5 °C/W 6
Junction-to-board characterization parameter ψJB 10 °C/W 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 3.8 °C/W 6
Junction-to-pad thermal resistance RθJP 3.58 °C/W 6
Random additive jitter tRJIT 0.124 ps, RMS fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.25 V, 10 kHz to 20 MHz 8
Random additive jitter tRJIT 0.178 ps, RMS fOUT = 100 MHz, VIN,SE = 0.9 V, Vth = 1.1 V, 10 kHz to 20 MHz 8
Random additive jitter tRJIT 0.061 ps, RMS fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V, VICM = 1 V, 10 kHz to 20 MHz 8
Random additive jitter tRJIT 0.119 ps, RMS fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V, VICM = 1 V, 10 kHz to 20 MHz 8
Random additive jitter tRJIT 0.104 ps, RMS fOUT = 100 MHz, VIN,DIFF,PP = 1 V, VICM = 1 V, 10 kHz to 20 MHz 8

CAD (KiCad official)

  • Symbol: CDCLVP2106RHAT
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: cdclvp2106rhat-etched.step / cdclvp2106rhat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdclvp2106rhat.step / cdclvp2106rhat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (34 pp, sha256 d3fc9f46e88b2284, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF