component
CDCLVD2102RGTT
Public Made by Adomby adom
Texas Instruments LVDS ICs, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "cdclvd2102rgtt",
"version": "0.1.0",
"type": "component",
"description": "Texas Instruments LVDS ICs, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"communication interface chip-uart-485-232",
"cdclvd2102rgtt",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
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"cdclvd2102rgtt.kicad_mod",
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"cdclvd2102rgtt.step",
"cdclvd2102rgtt.lbr",
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"docs/cdclvd2102rgtt-datasheet.pdf",
"viewers/symbol.html",
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"component": {
"mpn": "CDCLVD2102RGTT",
"manufacturer": "Texas Instruments",
"package": "VQFN-16-EP(3x3)",
"pin_count": 17,
"category": "Communication Interface Chip/UART/485/232",
"subcategory": "LVDS ICs",
"datasheet": "https://www.ti.com/cn/lit/gpn/cdclvd2102",
"parts": {
"symbol": "cdclvd2102rgtt.kicad_sym",
"footprint": "cdclvd2102rgtt.kicad_mod",
"model_3d": "cdclvd2102rgtt-hero.glb",
"model_3d_plain": "cdclvd2102rgtt.glb",
"model_3d_step": "cdclvd2102rgtt-etched.step",
"model_3d_step_plain": "cdclvd2102rgtt.step",
"lbr": "cdclvd2102rgtt.lbr"
},
"distributor_links": {
"lcsc": "C181598",
"digikey": "296-27612-2-ND",
"mouser": "595-CDCLVD2102RGTT"
},
"distributor_check": {
"checked_at": "2026-10-08T21:24:07Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "296-27612-2-ND",
"status": "found",
"lifecycle": "Active"
},
"mouser": {
"pn": "595-CDCLVD2102RGTT",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "GND",
"type": "power_in",
"description": "Device ground pin."
},
{
"number": "2",
"name": "EN",
"type": "input",
"description": "Output control pin with an internal 200 kΩ pull-up/pull-down: logic 0 disables all outputs, open enables all outputs, and logic 1 enables OUT0/OUT1 and disables OUT2/OUT3; thresholds are VIH = 0.7×VCC and VIL = 0.2×VCC."
},
{
"number": "3",
"name": "INP1",
"type": "input",
"description": "Positive side of the redundant input pair 1 (INP1/INN1), accepting LVDS, LVPECL or LVCMOS clock inputs with a differential clock input frequency up to 800 MHz."
},
{
"number": "4",
"name": "INN1",
"type": "input",
"description": "Negative side of the redundant input pair 1 (INP1/INN1); for single-ended operation the appropriate bias voltage (VAC_REF) should be applied to this unused negative input."
},
{
"number": "5",
"name": "VCC",
"type": "power_in",
"description": "2.5 V device supply pin; the device supply voltage range is 2.375 V to 2.625 V."
},
{
"number": "6",
"name": "INP0",
"type": "input",
"description": "Positive side of the input pair 0 (INP0/INN0), accepting LVDS, LVPECL or LVCMOS clock inputs with a differential clock input frequency up to 800 MHz."
},
{
"number": "7",
"name": "INN0",
"type": "input",
"description": "Negative side of the input pair 0 (INP0/INN0); for single-ended operation the appropriate bias voltage (VAC_REF) should be applied to this unused negative input."
},
{
"number": "8",
"name": "VAC_REF",
"type": "output",
"description": "Bias voltage output for capacitively coupled inputs, 1.1 V to 1.35 V (1.25 V typical) at 100 µA load with VCC = 2.5 V; a 0.1 µF capacitor to GND is recommended if used."
},
{
"number": "9",
"name": "OUTP0",
"type": "output",
"description": "Positive LVDS output of output pair 0, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A."
},
{
"number": "10",
"name": "OUTN0",
"type": "output",
"description": "Negative LVDS output of output pair 0, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A."
},
{
"number": "11",
"name": "OUTP1",
"type": "output",
"description": "Positive LVDS output of output pair 1, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A."
},
{
"number": "12",
"name": "OUTN1",
"type": "output",
"description": "Negative LVDS output of output pair 1, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A."
},
{
"number": "13",
"name": "OUTP2",
"type": "output",
"description": "Positive LVDS output of output pair 2, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A."
},
{
"number": "14",
"name": "OUTN2",
"type": "output",
"description": "Negative LVDS output of output pair 2, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A."
},
{
"number": "15",
"name": "OUTP3",
"type": "output",
"description": "Positive LVDS output of output pair 3, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A."
},
{
"number": "16",
"name": "OUTN3",
"type": "output",
"description": "Negative LVDS output of output pair 3, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A."
},
{
"number": "17",
"name": "Thermal Pad",
"type": "passive",
"description": "Exposed thermal pad that must be soldered to the PCB with a ground-plane thermal landing pattern and multiple vias for heat removal; die temperature should be limited to a maximum of 125°C."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The exposed thermal pad is not listed in the pin-function table. It is labeled 'EXPOSED PAD 17' only; The TOP VIEW pin map on page 2 is garbled in the text extraction, so pin numbers were taken from the; VAC_REF is listed as an output in the datasheet and typed accordingly. Its description is an enginee"
],
"pages_sent": 23,
"cost_usd": 0.0918,
"at": "2026-10-08T21:23:26"
},
"datasheet": {
"url": "https://www.ti.com/cn/lit/gpn/cdclvd2102",
"pages": 23,
"sha256": "4ffd5eed98c7ecca",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 17,
"described": 17,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
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"footprint": "viewers/footprint.html"
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"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
"checked": "2026-10-08",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cdclvd2102rgtt-etched.step",
"role": "eda",
"up": "Z",
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"sha256": "d05d9dc131d7bdb62e027d3609ed9ae023899b9f154a8ff3e8dbfbaf4299a279",
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}
}