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CDCLVD2102RGTT

Texas Instruments · LVDS ICs · VQFN-16-EP(3x3)

CDCLVD2102RGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground pin.
2 EN input Output control pin with an internal 200 kΩ pull-up/pull-down: logic 0 disables all outputs, open enables all outputs, and logic 1 enables OUT0/OUT1 and disables OUT2/OUT3; thresholds are VIH = 0.7×VCC and VIL = 0.2×VCC.
3 INP1 input Positive side of the redundant input pair 1 (INP1/INN1), accepting LVDS, LVPECL or LVCMOS clock inputs with a differential clock input frequency up to 800 MHz.
4 INN1 input Negative side of the redundant input pair 1 (INP1/INN1); for single-ended operation the appropriate bias voltage (VAC_REF) should be applied to this unused negative input.
5 VCC power_in 2.5 V device supply pin; the device supply voltage range is 2.375 V to 2.625 V.
6 INP0 input Positive side of the input pair 0 (INP0/INN0), accepting LVDS, LVPECL or LVCMOS clock inputs with a differential clock input frequency up to 800 MHz.
7 INN0 input Negative side of the input pair 0 (INP0/INN0); for single-ended operation the appropriate bias voltage (VAC_REF) should be applied to this unused negative input.
8 VAC_REF output Bias voltage output for capacitively coupled inputs, 1.1 V to 1.35 V (1.25 V typical) at 100 µA load with VCC = 2.5 V; a 0.1 µF capacitor to GND is recommended if used.
9 OUTP0 output Positive LVDS output of output pair 0, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A.
10 OUTN0 output Negative LVDS output of output pair 0, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A.
11 OUTP1 output Positive LVDS output of output pair 1, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A.
12 OUTN1 output Negative LVDS output of output pair 1, driven from input INP0/INN0, compatible with ANSI EIA/TIA-644A.
13 OUTP2 output Positive LVDS output of output pair 2, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A.
14 OUTN2 output Negative LVDS output of output pair 2, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A.
15 OUTP3 output Positive LVDS output of output pair 3, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A.
16 OUTN3 output Negative LVDS output of output pair 3, driven from input INP1/INN1, compatible with ANSI EIA/TIA-644A.
17 Thermal Pad passive Exposed thermal pad that must be soldered to the PCB with a ground-plane thermal landing pattern and multiple vias for heat removal; die temperature should be limited to a maximum of 125°C.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Communication Interface Chip/UART/485/232
Pins 17

CAD (KiCad official)

  • Symbol: CDCLVD2102RGTT
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: cdclvd2102rgtt-etched.step / cdclvd2102rgtt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdclvd2102rgtt.step / cdclvd2102rgtt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 4ffd5eed98c7ecca, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF