component
CDCLVD2102RGTR
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCDCLVD2102RGTR
Texas Instruments · Clock Buffers, Drivers, Distributors · VQFN-16-EP(3x3)
CDCLVD2102RGTR from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground for the 2.5 V supply domain. |
| 2 | EN | input | Output enable control with an internal 200 kΩ pull-up/pull-down: logic 0 disables all outputs, open enables all outputs, and logic 1 enables OUT0/OUT1 while disabling OUT2/OUT3. |
| 3 | INP1 | input | Positive input of the redundant differential input pair 1, accepting LVDS, LVPECL or LVCMOS (or single-ended) signals. |
| 4 | INN1 | input | Negative input of the redundant differential input pair 1; when driven single-ended, the unused negative input should be biased with VAC_REF. |
| 5 | VCC | power_in | 2.5 V device supply, recommended operating range 2.375 V to 2.625 V (2.5 V typical). |
| 6 | INP0 | input | Positive input of differential input pair 0 (IN0), accepting LVDS, LVPECL or LVCMOS (or single-ended) signals. |
| 7 | INN0 | input | Negative input of differential input pair 0; when driven single-ended, the unused negative input should be biased with VAC_REF. |
| 8 | VAC_REF | output | Bias voltage output (about 1.25 V, 1.1 V to 1.35 V at 100 µA) for capacitively coupled inputs; a 0.1 µF capacitor to GND is recommended when used. |
| 9 | OUTP0 | output | Positive LVDS output of pair 0 (ANSI EIA/TIA-644A compatible), driven from input IN0. |
| 10 | OUTN0 | output | Negative LVDS output of pair 0 (ANSI EIA/TIA-644A compatible), driven from input IN0. |
| 11 | OUTP1 | output | Positive LVDS output of pair 1 (ANSI EIA/TIA-644A compatible), driven from input IN0. |
| 12 | OUTN1 | output | Negative LVDS output of pair 1 (ANSI EIA/TIA-644A compatible), driven from input IN0. |
| 13 | OUTP2 | output | Positive LVDS output of pair 2 (ANSI EIA/TIA-644A compatible), driven from input IN1. |
| 14 | OUTN2 | output | Negative LVDS output of pair 2 (ANSI EIA/TIA-644A compatible), driven from input IN1. |
| 15 | OUTP3 | output | Positive LVDS output of pair 3 (ANSI EIA/TIA-644A compatible), driven from input IN1. |
| 16 | OUTN3 | output | Negative LVDS output of pair 3 (ANSI EIA/TIA-644A compatible), driven from input IN1. |
| 17 | Thermal Pad | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-16-EP(3x3) |
| Category | Clock/Timing |
| Pins | 17 |
CAD (KiCad official)
- Symbol:
CDCLVD2102RGTR - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
cdclvd2102rgtr-etched.step/cdclvd2102rgtr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdclvd2102rgtr.step/cdclvd2102rgtr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
4ffd5eed98c7ecca, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).