component

CDCLVD1213RGTT

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcdclvd1213rgttfactory-2.0.0extractor-text

Verified CDCLVD1213RGTT

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 17 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCLVD1213RGTT · VQFN-16-EP(3x3) · 17 pins
  • ✓copper: 17 copper pads, none touching another net
  • ✓datasheet: all 17 pin names found in the 25-page datasheet
  • ✓distributor: lcsc C701732, digikey 296-27761-2-ND, mouser 595-CDCLVD1213RGTT
  • ✓family: QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-tbdx02nz/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 17 pins = 17 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 17 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdclvd1213rgtt.kicad_sym✓ cdclvd1213rgtt.kicad_mod✓ cdclvd1213rgtt.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cdclvd1213rgtt: viewers · Ray
cdclvd1213rgtt-etched.glb Publish 0.1.0 · Ray
cdclvd1213rgtt-etched.step cdclvd1213rgtt: factory component page (tier=mfr) · Ray
cdclvd1213rgtt-hero.glb cdclvd1213rgtt: hero GLB from the etched model (keeps the MPN mark) · Ray
cdclvd1213rgtt-hero.overlay.json Publish 0.1.0 · Ray
cdclvd1213rgtt.glb Publish 0.1.0 · Ray
cdclvd1213rgtt.kicad_mod Publish 0.1.0 · Ray
cdclvd1213rgtt.kicad_sym Publish 0.1.0 · Ray
cdclvd1213rgtt.lbr Publish 0.1.0 · Ray
cdclvd1213rgtt.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 17 pins · Ray

CDCLVD1213RGTT

Texas Instruments · Clock Buffers, Drivers · VQFN-16-EP(3x3)

CDCLVD1213RGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground; the datasheet lists pins 1 and 9 as GND.
2 QDP output Differential divided LVDS output pair (true side) for the QD output, whose divide ratio is set by DIV to 1, 2 or 4.
3 QDN output Differential divided LVDS output pair (complement side) for the QD output, whose divide ratio is set by DIV to 1, 2 or 4.
4 DIV input Divider selection input with an internal 200-kΩ pullup and pulldown; DIV at 0 selects /1, open selects /2 and 1 selects /4.
5 VCC power_in 2.5-V device supply; the recommended range is 2.375 V to 2.625 V.
6 INN input Complementary differential clock input; the differential input voltage must be 0.3 V to 1.6 Vpp with VICM = 1.25 V.
7 INP input True differential clock input; the input frequency can be up to 800 MHz and the input common-mode range is 1 V to VCC - 0.3 V.
8 VT input Input for threshold voltage; with AC coupling an external bias of VCC/2 must be provided to this pin.
9 GND power_in Device ground; the datasheet lists pins 1 and 9 as GND.
10 VCC power_in 2.5-V device supply; the recommended range is 2.375 V to 2.625 V.
11 QP0 output Differential LVDS output pair 0 (true side), rated for 50-Ω lines with 100-Ω receiver termination.
12 QN0 output Differential LVDS output pair 0 (complement side), rated for 50-Ω lines with 100-Ω receiver termination.
13 QP1 output Differential LVDS output pair 1 (true side), rated for 50-Ω lines with 100-Ω receiver termination.
14 QN1 output Differential LVDS output pair 1 (complement side), rated for 50-Ω lines with 100-Ω receiver termination.
15 QP2 output Differential LVDS output pair 2 (true side), rated for 50-Ω lines with 100-Ω receiver termination.
16 QN2 output Differential LVDS output pair 2 (complement side), rated for 50-Ω lines with 100-Ω receiver termination.
17 Thermal Pad passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category RTC/Clock Chip
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.3 2.8 V 3
Storage temperature Tstg -65 150 °C 3
Device supply voltage VCC 2.375 2.5 2.625 V 4
Ambient temperature TA -40 85 °C 4
Input high current IdIH 30 μA VCC = 2.625 V, VIH = 2.625 V 4
Input low current IdIL -30 μA VCC = 2.625 V, VIL = 0 V 4
Input pullup or pulldown resistor Rpull(DIV) 200 kΩ 4
Input frequency fIN 800 MHz Clock input 4
Differential input voltage peak-to-peak VIN, DIFF 0.3 1.6 VPP VICM = 1.25 V 4
Input termination RIN 70 Ω INP, INN to VT, DC 4
Input high current IIH 10 μA VCC = 2.625 V, VIH = 2.625 V 4
Input low current IIL -10 μA VCC = 2.625 V, VIL = 0 V 4
Input edge rate ΔV/ΔT 0.75 V/ns 20% to 80% 4
Input capacitance CIN 2.5 pF 4
Thermal resistance junction-to-ambient RθJA 51.3 °C/W 4
Thermal resistance junction-to-case (top) RθJC(top) 85.4 °C/W 4
Thermal resistance junction-to-board RθJB 20.1 °C/W 4
Junction-to-top characterization parameter ψJT 1.3 °C/W 4
Junction-to-board characterization parameter ψJB 19.4 °C/W 4
Thermal resistance junction-to-case (bottom) RθJC(bot) 6 °C/W 4
Differential output voltage magnitude /VOD/ 250 450 mV VIN, DIFF, PP = 0.3 V, RL = 100 Ω 5
Change in differential output voltage magnitude ΔVOD -15 15 mV 5
Steady-state common-mode output voltage VOC(SS) 1.1 1.375 V 5
Steady-state common-mode output voltage change ΔVOC(SS) -15 15 mV VIN, DIFF, PP = 0.6 V, RL = 100 Ω 5
Short-circuit output current IOS -24 24 mA VOD = 0 V 5
Output AC common mode VOS 25 70 mVPP VIN, DIFF, PP = 0.6 V, RL = 100 Ω 5
Output overshoot and undershoot Vring 10 % Percentage of output amplitude VOD 5
Propagation delay tPD 1.5 2.5 ns VIN, DIFF, PP = 0.3 V 5
Part-to-part skew tSK, PP 600 ps 5
Output skew tSK, O 20 ps Undivided outputs only 5
Pulse skew (with 50% duty cycle input) tSK,P -50 50 ps Crossing-point-to-crossing-point distortion 5
Random additive jitter (with 50% duty cycle input) tRJIT 0.3 ps, RMS 10 kHz, 20 MHz, edge speed 0.75 V/ns 5
Output rise/fall time tR/tF 50 300 ps 20% to 80%, 100 Ω, 5 pF 5
Static supply current ICCSTAT 17 28 mA Outputs unterminated, f = 0 Hz 5
Supply current ICC100 40 58 mA All outputs, RL = 100 Ω, f = 100 MHz 5
Supply current ICC800 60 85 mA All outputs, RL = 100 Ω, f = 800 MHz 5

CAD (KiCad official)

  • Symbol: CDCLVD1213RGTT
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: cdclvd1213rgtt-etched.step / cdclvd1213rgtt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdclvd1213rgtt.step / cdclvd1213rgtt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 9c7bb615854d761c, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF