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CDCLVD1212RHAT
Public Made by Adomby adom
Texas Instruments Clock Buffers, Drivers, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CDCLVD1212RHAT
Texas Instruments · Clock Buffers, Drivers · VQFN-40-EP(6x6)
CDCLVD1212RHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN_SEL | input | Input selection pin: low selects INP0/INN0, high selects INP1/INN1, and leaving it open disables the outputs (static); it has an internal 200-kΩ pullup and pulldown. |
| 2 | INP1 | input | Positive side of differential redundant input pair 1 (or single-ended input), accepting LVDS, LVPECL, or LVCMOS levels with input frequency up to 800 MHz. |
| 3 | INN1 | input | Negative side of differential redundant input pair 1 (or single-ended input); when driven single-ended, the unused negative input must be biased to VAC_REF. |
| 4 | VAC_REF1 | output | Bias voltage output for capacitive-coupled inputs, 1.25 V typical (1.1 V to 1.35 V at VCC = 2.5 V, Iload = 100 µA); TI recommends a 0.1-µF capacitor to GND if used. |
| 5 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 6 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 7 | VAC_REF0 | output | Bias voltage output for capacitive-coupled inputs, 1.25 V typical (1.1 V to 1.35 V at VCC = 2.5 V, Iload = 100 µA); TI recommends a 0.1-µF capacitor to GND if used. |
| 8 | INN0 | input | Negative side of differential input pair 0 (or single-ended input); when driven single-ended, the unused negative input must be biased to VAC_REF. |
| 9 | INP0 | input | Positive side of differential input pair 0 (or single-ended input), accepting LVDS, LVPECL, or LVCMOS levels with input frequency up to 800 MHz. |
| 10 | N.C. | unconnected | No connect; not internally connected. |
| 11 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 12 | OUTP0 | output | Positive side of LVDS differential output pair 0, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 13 | OUTN0 | output | Negative side of LVDS differential output pair 0, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 14 | OUTP1 | output | Positive side of LVDS differential output pair 1, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 15 | OUTN1 | output | Negative side of LVDS differential output pair 1, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 16 | OUTP2 | output | Positive side of LVDS differential output pair 2, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 17 | OUTN2 | output | Negative side of LVDS differential output pair 2, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 18 | OUTP3 | output | Positive side of LVDS differential output pair 3, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 19 | OUTN3 | output | Negative side of LVDS differential output pair 3, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 20 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 21 | GND | power_in | Device ground; the thermal pad must also be soldered to ground. |
| 22 | OUTP4 | output | Positive side of LVDS differential output pair 4, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 23 | OUTN4 | output | Negative side of LVDS differential output pair 4, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 24 | OUTP5 | output | Positive side of LVDS differential output pair 5, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 25 | OUTN5 | output | Negative side of LVDS differential output pair 5, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 26 | OUTP6 | output | Positive side of LVDS differential output pair 6, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 27 | OUTN6 | output | Negative side of LVDS differential output pair 6, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 28 | OUTP7 | output | Positive side of LVDS differential output pair 7, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 29 | OUTN7 | output | Negative side of LVDS differential output pair 7, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 30 | GND | power_in | Device ground; the thermal pad must also be soldered to ground. |
| 31 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 32 | OUTP8 | output | Positive side of LVDS differential output pair 8, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 33 | OUTN8 | output | Negative side of LVDS differential output pair 8, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 34 | OUTP9 | output | Positive side of LVDS differential output pair 9, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 35 | OUTN9 | output | Negative side of LVDS differential output pair 9, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 36 | OUTP10 | output | Positive side of LVDS differential output pair 10, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 37 | OUTN10 | output | Negative side of LVDS differential output pair 10, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 38 | OUTP11 | output | Positive side of LVDS differential output pair 11, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 39 | OUTN11 | output | Negative side of LVDS differential output pair 11, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 40 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | RTC/Clock Chip |
| Pins | 41 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VCC | VCC | -0.3 | 2.8 | V | 4 | ||
| Input voltage, VI | VI | -0.2 | V | 4 | |||
| Output voltage, VO | VO | -0.2 | V | 4 | |||
| Storage temperature, Tstg | Tstg | -65 | 150 | °C | 4 | ||
| Device supply voltage | VCC | 2.375 | 2.5 | 2.625 | V | 4 | |
| Ambient temperature | TA | -40 | 85 | °C | 4 | ||
| Input high current | IdIH | 30 | μA | VCC = 2.625 V, VIH = 2.625 V | 5 | ||
| Input low current | IdIL | -30 | μA | VCC = 2.625 V, VIL = 0 V | 5 | ||
| Input threshold voltage | Vth | 1.1 | 1.5 | V | External threshold voltage applied to complementary input | 5 | |
| Differential input voltage peak-to-peak | VIN,DIFF | 0.3 | 1.6 | VPP | VICM = 1.25 V | 5 | |
| Input common-mode voltage range | VICM | 1 | V | VIN,DIFF,PP > 0.4 V | 5 | ||
| Input high current (differential input) | IIH | 10 | μA | VCC = 2.625 V, VIH = 2.625 V | 5 | ||
| Input low current (differential input) | IIL | -10 | μA | VCC = 2.625, VIL = 0 V | 5 | ||
| Differential output voltage magnitude | /VOD/ | 250 | 450 | mV | VIN,DIFF,PP = 0.3 V, RL = 100 Ω | 5 | |
| Change in differential output voltage magnitude | ΔVOD | -15 | 15 | mV | 5 | ||
| Steady-state common-mode output voltage | VOC(SS) | 1.1 | 1.375 | V | 5 | ||
| Change in steady-state common-mode output voltage | ΔVOC(SS) | -15 | 15 | mV | VIN,DIFF,PP = 0.6 V, RL = 100 Ω | 5 | |
| Output AC common mode | VOS | 40 | 70 | mVPP | VIN,DIFF,PP = 0.6 V, RL = 100 Ω | 5 | |
| Short-circuit output current | IOS | -24 | 24 | mA | VOD = 0 V | 5 | |
| Propagation delay | tPD | 1.5 | 2.5 | ns | VIN,DIFF,PP = 0.3 V | 5 | |
| Output skew | tSK,O | 35 | ps | 5 | |||
| Pulse skew (with 50% duty cycle input) | tSK,P | -50 | 50 | ps | Crossing-point-to-crossing-point distortion, with 50% duty cycle input | 5 | |
| Output rise/fall time | tR/tF | 50 | 300 | ps | 20% to 80%, 100 Ω, 5 pF | 5 | |
| Static supply current | ICCSTAT | 17 | 28 | mA | Outputs unterminated, f = 0 Hz | 5 | |
| Supply current, 100 MHz | ICC100 | 85 | 110 | mA | All outputs, RL = 100 Ω, f = 100 MHz | 5 | |
| Supply current, 800 MHz | ICC800 | 117 | 146 | mA | All outputs, RL = 100 Ω, f = 800 MHz | 5 | |
| Reference output voltage | VAC_REF | 1.1 | 1.25 | 1.35 | V | VCC = 2.5 V, Iload = 100 µA | 6 |
| Junction-to-ambient thermal resistance | RθJA | 31 | °C/W | RHA (VQFN) 40 pins | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 28.7 | °C/W | RHA (VQFN) 40 pins | 4 | ||
| Junction-to-board thermal resistance | RθJB | 9.3 | °C/W | RHA (VQFN) 40 pins | 4 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 3.1 | °C/W | RHA (VQFN) 40 pins | 4 |
CAD (KiCad official)
- Symbol:
CDCLVD1212RHAT - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
cdclvd1212rhat-etched.step/cdclvd1212rhat-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdclvd1212rhat.step/cdclvd1212rhat.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
71e1d7c62a5fc622, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CDCLVD1212RHAT
**Texas Instruments** · Clock Buffers, Drivers · VQFN-40-EP(6x6)
CDCLVD1212RHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN_SEL | input | Input selection pin: low selects INP0/INN0, high selects INP1/INN1, and leaving it open disables the outputs (static); it has an internal 200-kΩ pullup and pulldown. |
| 2 | INP1 | input | Positive side of differential redundant input pair 1 (or single-ended input), accepting LVDS, LVPECL, or LVCMOS levels with input frequency up to 800 MHz. |
| 3 | INN1 | input | Negative side of differential redundant input pair 1 (or single-ended input); when driven single-ended, the unused negative input must be biased to VAC_REF. |
| 4 | VAC_REF1 | output | Bias voltage output for capacitive-coupled inputs, 1.25 V typical (1.1 V to 1.35 V at VCC = 2.5 V, Iload = 100 µA); TI recommends a 0.1-µF capacitor to GND if used. |
| 5 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 6 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 7 | VAC_REF0 | output | Bias voltage output for capacitive-coupled inputs, 1.25 V typical (1.1 V to 1.35 V at VCC = 2.5 V, Iload = 100 µA); TI recommends a 0.1-µF capacitor to GND if used. |
| 8 | INN0 | input | Negative side of differential input pair 0 (or single-ended input); when driven single-ended, the unused negative input must be biased to VAC_REF. |
| 9 | INP0 | input | Positive side of differential input pair 0 (or single-ended input), accepting LVDS, LVPECL, or LVCMOS levels with input frequency up to 800 MHz. |
| 10 | N.C. | unconnected | No connect; not internally connected. |
| 11 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 12 | OUTP0 | output | Positive side of LVDS differential output pair 0, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 13 | OUTN0 | output | Negative side of LVDS differential output pair 0, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 14 | OUTP1 | output | Positive side of LVDS differential output pair 1, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 15 | OUTN1 | output | Negative side of LVDS differential output pair 1, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 16 | OUTP2 | output | Positive side of LVDS differential output pair 2, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 17 | OUTN2 | output | Negative side of LVDS differential output pair 2, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 18 | OUTP3 | output | Positive side of LVDS differential output pair 3, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 19 | OUTN3 | output | Negative side of LVDS differential output pair 3, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 20 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 21 | GND | power_in | Device ground; the thermal pad must also be soldered to ground. |
| 22 | OUTP4 | output | Positive side of LVDS differential output pair 4, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 23 | OUTN4 | output | Negative side of LVDS differential output pair 4, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 24 | OUTP5 | output | Positive side of LVDS differential output pair 5, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 25 | OUTN5 | output | Negative side of LVDS differential output pair 5, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 26 | OUTP6 | output | Positive side of LVDS differential output pair 6, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 27 | OUTN6 | output | Negative side of LVDS differential output pair 6, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 28 | OUTP7 | output | Positive side of LVDS differential output pair 7, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 29 | OUTN7 | output | Negative side of LVDS differential output pair 7, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 30 | GND | power_in | Device ground; the thermal pad must also be soldered to ground. |
| 31 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 32 | OUTP8 | output | Positive side of LVDS differential output pair 8, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 33 | OUTN8 | output | Negative side of LVDS differential output pair 8, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 34 | OUTP9 | output | Positive side of LVDS differential output pair 9, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 35 | OUTN9 | output | Negative side of LVDS differential output pair 9, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 36 | OUTP10 | output | Positive side of LVDS differential output pair 10, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 37 | OUTN10 | output | Negative side of LVDS differential output pair 10, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 38 | OUTP11 | output | Positive side of LVDS differential output pair 11, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 39 | OUTN11 | output | Negative side of LVDS differential output pair 11, ANSI EIA/TIA-644A compatible; unused outputs may be left open. |
| 40 | VCC | power_in | 2.5-V device supply, specified from 2.375 V to 2.625 V. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | RTC/Clock Chip |
| Pins | 41 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VCC | VCC | -0.3 | | 2.8 | V | | 4 |
| Input voltage, VI | VI | -0.2 | | | V | | 4 |
| Output voltage, VO | VO | -0.2 | | | V | | 4 |
| Storage temperature, Tstg | Tstg | -65 | | 150 | °C | | 4 |
| Device supply voltage | VCC | 2.375 | 2.5 | 2.625 | V | | 4 |
| Ambient temperature | TA | -40 | | 85 | °C | | 4 |
| Input high current | IdIH | | | 30 | μA | VCC = 2.625 V, VIH = 2.625 V | 5 |
| Input low current | IdIL | -30 | | | μA | VCC = 2.625 V, VIL = 0 V | 5 |
| Input threshold voltage | Vth | 1.1 | | 1.5 | V | External threshold voltage applied to complementary input | 5 |
| Differential input voltage peak-to-peak | VIN,DIFF | 0.3 | | 1.6 | VPP | VICM = 1.25 V | 5 |
| Input common-mode voltage range | VICM | 1 | | | V | VIN,DIFF,PP > 0.4 V | 5 |
| Input high current (differential input) | IIH | | | 10 | μA | VCC = 2.625 V, VIH = 2.625 V | 5 |
| Input low current (differential input) | IIL | -10 | | | μA | VCC = 2.625, VIL = 0 V | 5 |
| Differential output voltage magnitude | /VOD/ | 250 | | 450 | mV | VIN,DIFF,PP = 0.3 V, RL = 100 Ω | 5 |
| Change in differential output voltage magnitude | ΔVOD | -15 | | 15 | mV | | 5 |
| Steady-state common-mode output voltage | VOC(SS) | 1.1 | | 1.375 | V | | 5 |
| Change in steady-state common-mode output voltage | ΔVOC(SS) | -15 | | 15 | mV | VIN,DIFF,PP = 0.6 V, RL = 100 Ω | 5 |
| Output AC common mode | VOS | 40 | | 70 | mVPP | VIN,DIFF,PP = 0.6 V, RL = 100 Ω | 5 |
| Short-circuit output current | IOS | -24 | | 24 | mA | VOD = 0 V | 5 |
| Propagation delay | tPD | 1.5 | | 2.5 | ns | VIN,DIFF,PP = 0.3 V | 5 |
| Output skew | tSK,O | | | 35 | ps | | 5 |
| Pulse skew (with 50% duty cycle input) | tSK,P | -50 | | 50 | ps | Crossing-point-to-crossing-point distortion, with 50% duty cycle input | 5 |
| Output rise/fall time | tR/tF | 50 | | 300 | ps | 20% to 80%, 100 Ω, 5 pF | 5 |
| Static supply current | ICCSTAT | | 17 | 28 | mA | Outputs unterminated, f = 0 Hz | 5 |
| Supply current, 100 MHz | ICC100 | | 85 | 110 | mA | All outputs, RL = 100 Ω, f = 100 MHz | 5 |
| Supply current, 800 MHz | ICC800 | | 117 | 146 | mA | All outputs, RL = 100 Ω, f = 800 MHz | 5 |
| Reference output voltage | VAC_REF | 1.1 | 1.25 | 1.35 | V | VCC = 2.5 V, Iload = 100 µA | 6 |
| Junction-to-ambient thermal resistance | RθJA | | 31 | | °C/W | RHA (VQFN) 40 pins | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 28.7 | | °C/W | RHA (VQFN) 40 pins | 4 |
| Junction-to-board thermal resistance | RθJB | | 9.3 | | °C/W | RHA (VQFN) 40 pins | 4 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | | 3.1 | | °C/W | RHA (VQFN) 40 pins | 4 |
## CAD (KiCad official)
- Symbol: `CDCLVD1212RHAT`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `cdclvd1212rhat-etched.step` / `cdclvd1212rhat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdclvd1212rhat.step` / `cdclvd1212rhat.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdclvd1212) (23 pp, sha256 `71e1d7c62a5fc622`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cdclvd1212rhat-datasheet.pdf)