component

CDCLVD1212RHAR

Public Made by Adom

by adom

Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timingcdclvd1212rharfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

CDCLVD1212RHAR

Texas Instruments · Clock Buffers, Drivers, Distributors · VQFN-40-EP(6x6)

CDCLVD1212RHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN_SEL input Input selection pin that chooses which clock input (IN0 or IN1) is routed to the outputs; it has an internal 200-kΩ pullup and pulldown, and leaving it open disables the outputs (static).
2 INP1 input Positive side of the redundant differential input pair 1, which can also be used as a single-ended input; the part accepts LVDS, LVPECL, or LVCMOS inputs.
3 INN1 input Negative side of the redundant differential input pair 1; in single-ended operation the appropriate bias voltage VAC_REF must be applied to this unused negative input.
4 VAC_REF1 output Bias voltage output for capacitively coupled inputs; if used, TI recommends a 0.1-µF capacitor to GND on this pin.
5 VCC power_in 2.5-V device supply; recommended range is 2.375 V to 2.625 V.
6 VCC power_in 2.5-V device supply; recommended range is 2.375 V to 2.625 V.
7 VAC_REF0 output Bias voltage output for capacitively coupled inputs; if used, TI recommends a 0.1-µF capacitor to GND on this pin.
8 INN0 input Negative side of the differential input pair 0, which can also be used as a single-ended input with VAC_REF applied to the unused pin.
9 INP0 input Positive side of the differential input pair 0, which can also be used as a single-ended input; the part accepts LVDS, LVPECL, or LVCMOS inputs.
10 N.C. unconnected No connect; this pin is not internally connected.
11 VCC power_in 2.5-V device supply; recommended range is 2.375 V to 2.625 V.
12 OUTP0 output Positive side of LVDS differential output pair 0, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
13 OUTN0 output Negative side of LVDS differential output pair 0, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
14 OUTP1 output Positive side of LVDS differential output pair 1, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
15 OUTN1 output Negative side of LVDS differential output pair 1, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
16 OUTP2 output Positive side of LVDS differential output pair 2, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
17 OUTN2 output Negative side of LVDS differential output pair 2, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
18 OUTP3 output Positive side of LVDS differential output pair 3, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
19 OUTN3 output Negative side of LVDS differential output pair 3, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
20 VCC power_in 2.5-V device supply; recommended range is 2.375 V to 2.625 V.
21 GND power_in Device ground; must be connected to the thermal pad ground.
22 OUTP4 output Positive side of LVDS differential output pair 4, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
23 OUTN4 output Negative side of LVDS differential output pair 4, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
24 OUTP5 output Positive side of LVDS differential output pair 5, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
25 OUTN5 output Negative side of LVDS differential output pair 5, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
26 OUTP6 output Positive side of LVDS differential output pair 6, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
27 OUTN6 output Negative side of LVDS differential output pair 6, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
28 OUTP7 output Positive side of LVDS differential output pair 7, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
29 OUTN7 output Negative side of LVDS differential output pair 7, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
30 GND power_in Device ground; must be connected to the thermal pad ground.
31 VCC power_in 2.5-V device supply; recommended range is 2.375 V to 2.625 V.
32 OUTP8 output Positive side of LVDS differential output pair 8, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
33 OUTN8 output Negative side of LVDS differential output pair 8, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
34 OUTP9 output Positive side of LVDS differential output pair 9, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
35 OUTN9 output Negative side of LVDS differential output pair 9, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
36 OUTP10 output Positive side of LVDS differential output pair 10, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
37 OUTN10 output Negative side of LVDS differential output pair 10, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
38 OUTP11 output Positive side of LVDS differential output pair 11, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
39 OUTN11 output Negative side of LVDS differential output pair 11, ANSI EIA/TIA-644A compatible; the output can handle a permanent short.
40 VCC power_in 2.5-V device supply; recommended range is 2.375 V to 2.625 V.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Clock/Timing
Pins 41

CAD (KiCad official)

  • Symbol: CDCLVD1212RHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: cdclvd1212rhar-etched.step / cdclvd1212rhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdclvd1212rhar.step / cdclvd1212rhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 5074ca131810290a, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF