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CDCLVD1208RHDT

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Texas Instruments Clock Buffers, Drivers, Distributors, VQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CDCLVD1208RHDT

Texas Instruments · Clock Buffers, Drivers, Distributors · VQFN-28-EP(5x5)

CDCLVD1208RHDT from Texas Instruments, in a VQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground.
2 OUTP7 output Differential LVDS output pair 7, positive leg, ANSI EIA/TIA-644A compatible.
3 OUTN7 output Differential LVDS output pair 7, negative leg, ANSI EIA/TIA-644A compatible.
4 IN_SEL input Input selection pin with an internal 200-kΩ pullup and pulldown; it selects the active input per Table 1 (0 = INP0/INN0, 1 = INP1/INN1), and leaving it open disables the input buffers and holds the outputs static.
5 INP1 input Differential redundant input pair 1, positive leg, or single-ended input.
6 INN1 input Differential redundant input pair 1, negative leg, or single-ended input; when used single-ended, the bias voltage VAC_REF must be applied to this unused negative input.
7 VAC_REF1 output Bias voltage output for capacitive-coupled inputs; if used, TI recommends a 0.1-µF capacitor to GND on this pin.
8 VCC power_in 2.5-V supply for the device.
9 INP0 input Differential input pair 0, positive leg, or single-ended input.
10 INN0 input Differential input pair 0, negative leg, or single-ended input; when used single-ended, the bias voltage VAC_REF must be applied to this unused negative input.
11 VAC_REF0 output Bias voltage output for capacitive-coupled inputs; if used, TI recommends a 0.1-µF capacitor to GND on this pin.
12 OUTP0 output Differential LVDS output pair 0, positive leg.
13 OUTN0 output Differential LVDS output pair 0, negative leg.
14 GND power_in Device ground.
15 VCC power_in 2.5-V supply for the device.
16 OUTP1 output Differential LVDS output pair 1, positive leg.
17 OUTN1 output Differential LVDS output pair 1, negative leg.
18 OUTP2 output Differential LVDS output pair 2, positive leg.
19 OUTN2 output Differential LVDS output pair 2, negative leg.
20 OUTP3 output Differential LVDS output pair 3, positive leg.
21 OUTN3 output Differential LVDS output pair 3, negative leg.
22 OUTP4 output Differential LVDS output pair 4, positive leg.
23 OUTN4 output Differential LVDS output pair 4, negative leg.
24 OUTP5 output Differential LVDS output pair 5, positive leg.
25 OUTN5 output Differential LVDS output pair 5, negative leg.
26 OUTP6 output Differential LVDS output pair 6, positive leg.
27 OUTN6 output Differential LVDS output pair 6, negative leg.
28 VCC power_in 2.5-V supply for the device.
29 Thermal pad (exposed pad) passive Exposed thermal pad that must be soldered to the printed circuit board for thermal and mechanical performance; the datasheet does not state an electrical connection for it.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-28-EP(5x5)
Category Clock/Timing
Pins 29

CAD (KiCad official)

  • Symbol: CDCLVD1208RHDT
  • Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
  • 3D model: VQFN-28-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: cdclvd1208rhdt-etched.step / cdclvd1208rhdt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdclvd1208rhdt.step / cdclvd1208rhdt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 66aef596b66ebcee, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF