CDCLVD1204RGTR

{
  "schema_version": 1,
  "type": "component",
  "slug": "cdclvd1204rgtr",
  "title": "CDCLVD1204RGTR",
  "brief": "Texas Instruments Clock Buffers, Drivers, Distributors, QFN-16-EP(3x3). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "clock-timing",
    "cdclvd1204rgtr"
  ],
  "component": {
    "mpn": "CDCLVD1204RGTR",
    "manufacturer": "Texas Instruments",
    "package": "QFN-16-EP(3x3)",
    "pin_count": 17,
    "category": "Clock/Timing",
    "subcategory": "Clock Buffers, Drivers, Distributors",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cdclvd1204.pdf",
    "parts": {
      "symbol": "cdclvd1204rgtr.kicad_sym",
      "footprint": "cdclvd1204rgtr.kicad_mod",
      "model_3d": "cdclvd1204rgtr-etched.glb",
      "model_3d_plain": "cdclvd1204rgtr.glb",
      "model_3d_step": "cdclvd1204rgtr-etched.step",
      "model_3d_step_plain": "cdclvd1204rgtr.step",
      "lbr": "cdclvd1204rgtr.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground."
      },
      {
        "number": "2",
        "name": "IN_SEL",
        "type": "input",
        "description": "Input selection with an internal 200-kΩ pullup and pulldown; selects which input port (IN0 or IN1) is routed to the outputs. If left open (mid-level), outputs are disabled (static) for fail-safe operation."
      },
      {
        "number": "3",
        "name": "INP1",
        "type": "input",
        "description": "Positive side of differential clock input pair 1 (redundant input pair or single-ended input). Accepts LVDS, LVPECL, or LVCMOS up to 800 MHz differential."
      },
      {
        "number": "4",
        "name": "INN1",
        "type": "input",
        "description": "Negative side of differential clock input pair 1 (redundant input pair or single-ended input). When used single-ended, VAC_REF must be applied to this pin."
      },
      {
        "number": "5",
        "name": "VCC",
        "type": "power_in",
        "description": "2.5-V supply for the device (recommended range 2.375 V to 2.625 V)."
      },
      {
        "number": "6",
        "name": "INP0",
        "type": "input",
        "description": "Positive side of differential clock input pair 0 (redundant input pair or single-ended input). Accepts LVDS, LVPECL, or LVCMOS up to 800 MHz differential."
      },
      {
        "number": "7",
        "name": "INN0",
        "type": "input",
        "description": "Negative side of differential clock input pair 0 (redundant input pair or single-ended input). When used single-ended, VAC_REF must be applied to this pin."
      },
      {
        "number": "8",
        "name": "VAC_REF",
        "type": "output",
        "description": "Bias voltage output for capacitive-coupled inputs. TI recommends a 0.1-µF bypass capacitor from this pin to GND. Used to bias the unused negative input pin in single-ended input mode."
      },
      {
        "number": "9",
        "name": "OUTP0",
        "type": "output",
        "description": "Positive side of LVDS differential output pair 0 (ANSI EIA/TIA-644A compatible). Typical |VOD| = 250-450 mV into 100-Ω differential load."
      },
      {
        "number": "10",
        "name": "OUTN0",
        "type": "output",
        "description": "Negative side of LVDS differential output pair 0 (ANSI EIA/TIA-644A compatible)."
      },
      {
        "number": "11",
        "name": "OUTP1",
        "type": "output",
        "description": "Positive side of LVDS differential output pair 1 (ANSI EIA/TIA-644A compatible)."
      },
      {
        "number": "12",
        "name": "OUTN1",
        "type": "output",
        "description": "Negative side of LVDS differential output pair 1 (ANSI EIA/TIA-644A compatible)."
      },
      {
        "number": "13",
        "name": "OUTP2",
        "type": "output",
        "description": "Positive side of LVDS differential output pair 2 (ANSI EIA/TIA-644A compatible)."
      },
      {
        "number": "14",
        "name": "OUTN2",
        "type": "output",
        "description": "Negative side of LVDS differential output pair 2 (ANSI EIA/TIA-644A compatible)."
      },
      {
        "number": "15",
        "name": "OUTP3",
        "type": "output",
        "description": "Positive side of LVDS differential output pair 3 (ANSI EIA/TIA-644A compatible)."
      },
      {
        "number": "16",
        "name": "OUTN3",
        "type": "output",
        "description": "Negative side of LVDS differential output pair 3 (ANSI EIA/TIA-644A compatible)."
      },
      {
        "number": "17",
        "name": "Thermal Pad",
        "type": "power_in",
        "description": "Exposed thermal pad on the bottom of the VQFN package. Must be soldered to the PCB ground plane for proper thermal and electrical performance."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cdclvd1204.pdf",
        "pages": 28,
        "sha256": "1218e131aa4118f0",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          3,
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        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cdclvd1204rgtr-etched.step",
        "role": "eda",
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        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
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        "sha256": "b6ee4d937943ab8dee0182a85ae0a9aaa2a8a2d422f655fe61b3fbcbc2a7992b",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "QFN-16-EP(3x3)",
      "Category": "Clock/Timing",
      "Pins": "17"
    }
  },
  "variants": [
    {
      "mpn": "CDCLVD1204RGTR",
      "kind": "packaging"
    },
    {
      "mpn": "CDCLVD1204RGTRRGTT",
      "kind": "packaging"
    }
  ],
  "sections": [
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  "discovery_triggers": [
    "cdclvd1204rgtr"
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  "discovery_pitch": "CDCLVD1204RGTR (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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  "files": [
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    "cdclvd1204rgtr.lbr",
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  "visibility": {
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  "updated_at": "2026-09-24T18:59:06.202Z"
}