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CDCLVC1112PWR

Public Made by Adom

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Texas Instruments Clock Buffers, Drivers, Distributors, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock-timingcdclvc1112pwrfactory-2.0.0extractor-text

Verified CDCLVC1112PWR

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier mfr, 24 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCLVC1112PWR · TSSOP-24 · 24 pins
  • ✓copper: 24 copper pads, none touching another net
  • ✓datasheet: all 24 pin names found in the 37-page datasheet
  • ✓distributor: lcsc C2876940, digikey 296-27517-2-ND, mouser 595-CDCLVC1112PWR
  • ✓family: TSSOP-24_4.4x7.8mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-q1xtb6ea/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 24 pins = 24 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 24 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdclvc1112pwr.kicad_sym✓ cdclvc1112pwr.kicad_mod✓ cdclvc1112pwr.step
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Ray Publish 0.1.0 94cf03e 5h ago

CDCLVC1112PWR

Texas Instruments · Clock Buffers, Drivers, Distributors · TSSOP-24

CDCLVC1112PWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKIN input LVCMOS clock input, with a DC to 250 MHz frequency range at VDD 3.0 V to 3.6 V and DC to 180 MHz at VDD 2.3 V to 2.7 V.
2 1G input Asynchronous output enable control that switches all outputs into a low state when 1G is low.
3 Y0 output LVCMOS clock output; unused outputs can be left floating.
4 GND power_in Device ground.
5 VDD power_in Power 2.5-V or 3.3-V device supply.
6 Y4 output LVCMOS clock output; unused outputs can be left floating.
7 GND power_in Device ground.
8 Y6 output LVCMOS clock output; unused outputs can be left floating.
9 VDD power_in Power 2.5-V or 3.3-V device supply.
10 Y9 output LVCMOS clock output; unused outputs can be left floating.
11 GND power_in Device ground.
12 Y11 output LVCMOS clock output; unused outputs can be left floating.
13 VDD power_in Power 2.5-V or 3.3-V device supply.
14 Y10 output LVCMOS clock output; unused outputs can be left floating.
15 GND power_in Device ground.
16 Y8 output LVCMOS clock output; unused outputs can be left floating.
17 Y7 output LVCMOS clock output; unused outputs can be left floating.
18 VDD power_in Power 2.5-V or 3.3-V device supply.
19 Y5 output LVCMOS clock output; unused outputs can be left floating.
20 GND power_in Device ground.
21 Y2 output LVCMOS clock output; unused outputs can be left floating.
22 VDD power_in Power 2.5-V or 3.3-V device supply.
23 Y3 output LVCMOS clock output; unused outputs can be left floating.
24 Y1 output LVCMOS clock output; unused outputs can be left floating.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-24
Category Clock/Timing
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 4.6 V 5
Input voltage VIN -0.5 V 5
Output voltage VO -0.5 V 5
Input current IIN -20 20 mA 5
Continuous output current IO -50 50 mA 5
Maximum junction temperature TJ 125 °C 5
Storage temperature Tstg -65 150 °C 5
Supply voltage, 3.3-V supply VDD 3 3.3 3.6 V 3.3-V supply 5
Supply voltage, 2.5-V supply VDD 2.3 2.5 2.7 V 2.5-V supply 5
Input slew rate tr/tf 1 4 V/ns 5
Minimum pulse width at CLKIN tw 1.8 ns VDD = 3.0 V to 3.6 V 5
Minimum pulse width at CLKIN tw 2.75 ns VDD = 2.3 V to 2.7 V 5
LVCMOS clock input frequency fCLK 250 MHz VDD = 3.0 V to 3.6 V 5
LVCMOS clock input frequency fCLK 180 MHz VDD = 2.3 V to 2.7 V 5
Operating free-air temperature TA -40 85 °C 5
Static device current, 3.6 V IDD 6 10 mA 1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V 6
Static device current, 2.7 V IDD 3 6 mA 1G = VDD; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 2.7 V 6
Power-down current IPD 60 µA 1G = 0 V; CLKIN = 0 V or VDD; IO = 0 mA; VDD = 3.6 V or 2.7 V 6
Input leakage current at 1G II 8 µA VI = 0 V or VDD, VDD = 3.6 V or 2.7 V 6
Input leakage current at CLKIN II 25 µA VI = 0 V or VDD, VDD = 3.6 V or 2.7 V 6
Power dissipation capacitance per output CPD 6 pF VDD = 3.3 V; f = 10 MHz 6
Power dissipation capacitance per output CPD 4.5 pF VDD = 2.5 V; f = 10 MHz 6
Output frequency fOUT 250 MHz VDD = 3 V to 3.6 V 6
Output frequency fOUT 180 MHz VDD = 2.3 V to 2.7 V 6
High-level output voltage, 3.3 V VOH 2.9 V VDD = 3 V, IOH = -0.1 mA 6
High-level output voltage, 3.3 V VOH 2.5 V VDD = 3 V, IOH = -8 mA 6
High-level output voltage, 3.3 V VOH 2.2 V VDD = 3 V, IOH = -12 mA 6
Low-level output voltage, 3.3 V VOL 0.1 V VDD = 3 V, IOL = 0.1 mA 6
Low-level output voltage, 3.3 V VOL 0.5 V VDD = 3 V, IOL = 8 mA 6
Low-level output voltage, 3.3 V VOL 0.8 V VDD = 3 V, IOL = 12 mA 6
High-level output voltage, 2.5 V VOH 2.2 V VDD = 2.3 V, IOH = -0.1 mA 6
High-level output voltage, 2.5 V VOH 1.7 V VDD = 2.3 V, IOH = -8 mA 6
Low-level output voltage, 2.5 V VOL 0.1 V VDD = 2.3 V, IOL = 0.1 mA 6
Low-level output voltage, 2.5 V VOL 0.5 V VDD = 2.3 V, IOL = 8 mA 6
Propagation delay CLKIN to Yn, 3.3 V tPLH, tPHL 0.8 2 ns CLKIN to Yn 7
Output skew, 3.3 V tsk(o) 50 ps Equal load of each output 7
Rise and fall time, 3.3 V tr/tf 0.3 0.8 ns 20%-80% (VOH - VOL) 7
Output disable time, 3.3 V tDIS 6 ns 1G to Yn 7
Output enable time, 3.3 V tEN 6 ns 1G to Yn 7
Pulse skew, 3.3 V tsk(p) 180 ps To be measured with input duty cycle of 50% 7
Part-to-part skew, 3.3 V tsk(pp) 0.5 ns Under equal operating conditions for two parts 7
Additive jitter rms, 3.3 V tjitter 100 fs 12 kHz to 20 MHz, fOUT = 250 MHz 7
Propagation delay CLKIN to Yn, 2.5 V tPLH, tPHL 1 2.6 ns CLKIN to Yn 7
Output skew, 2.5 V tsk(o) 50 ps Equal load of each output 7
Rise and fall time, 2.5 V tr/tf 0.3 1.2 ns 20%-80% reference point 7
Output disable time, 2.5 V tDIS 10 ns 1G to Yn 7
Output enable time, 2.5 V tEN 10 ns 1G to Yn 7
Pulse skew, 2.5 V tsk(p) 220 ps To be measured with input duty cycle of 50% 7
Part-to-part skew, 2.5 V tsk(pp) 1.2 ns Under equal operating conditions for two parts 7
Additive jitter rms, 2.5 V tjitter 350 fs 12 kHz to 20 MHz, fOUT = 180 MHz 7
Junction-to-ambient thermal resistance, 24-pin TSSOP RθJA 87.9 °C/W Natural convection, JEDEC high-K board 6
Junction-to-case (top) thermal resistance, 24-pin TSSOP RθJC(top) 26.5 °C/W Cold plate test on package top 6

CAD (KiCad official)

  • Symbol: CDCLVC1112PWR
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cdclvc1112pwr-etched.step / cdclvc1112pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdclvc1112pwr.step / cdclvc1112pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (37 pp, sha256 7b5ccb44b8bc0016, retrieved 2026-11-06, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF