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CDCEL937PWR
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# CDCEL937PWR++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-20++CDCEL937PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Xin/CLK | input | Crystal oscillator input or LVCMOS clock input, selectable through the SDA/SCL bus. |+| 2 | S0 | input | User-programmable LVCMOS control input S0 with internal 500k pullup; in default mode it switches all outputs ON or OFF. |+| 3 | VDD | power_in | 1.8V power supply for the device. |+| 4 | VCtrl | input | VCXO control voltage input; leave open or pull up (approximately 500k) when not used. |+| 5 | GND | power_in | Ground. |+| 6 | Vddout | power_in | Output supply for all outputs; 1.8V for CDCEL937 (this pin is one of three Vddout pins, 6, 10 and 13). |+| 7 | Y4 | output | LVCMOS output Y4. |+| 8 | Y5 | output | LVCMOS output Y5. |+| 9 | GND | power_in | Ground. |+| 10 | Vddout | power_in | Output supply for all outputs; 1.8V for CDCEL937 (one of three Vddout pins, 6, 10 and 13). |+| 11 | Y7 | output | LVCMOS output Y7. |+| 12 | Y6 | output | LVCMOS output Y6. |+| 13 | Vddout | power_in | Output supply for all outputs; 1.8V for CDCEL937 (one of three Vddout pins, 6, 10 and 13). |+| 14 | Y3 | output | LVCMOS output Y3. |+| 15 | Y2 | output | LVCMOS output Y2. |+| 16 | GND | power_in | Ground. |+| 17 | Y1 | output | LVCMOS output Y1; its state (power down, 3-state, low or active) is user-definable in the Generic Configuration Register. |+| 18 | SCL/S2 | bidirectional | Serial clock input SCL in default configuration (LVCMOS, internal 500k pullup); can be reprogrammed as user control input S2. |+| 19 | SDA/S1 | bidirectional | Bidirectional serial data SDA in default configuration (LVCMOS, internal 500k pullup); can be reprogrammed as user control input S1. |+| 20 | Xout | output | Crystal oscillator output; leave open or pull up (approximately 500k) when not used. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Clock/Timing |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `CDCEL937PWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `cdcel937pwr-etched.step` / `cdcel937pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcel937pwr.step` / `cdcel937pwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdcel937.pdf) (39 pp, sha256 `c538114a66321dcf`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdcel937pwr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdcel937pwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdcel937pwr.kicad_sym",+ "cdcel937pwr.kicad_mod",+ "cdcel937pwr.glb",+ "cdcel937pwr.step",+ "cdcel937pwr.lbr",+ "docs/hero.png",+ "docs/cdcel937pwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cdcel937pwr-hero.glb",+ "cdcel937pwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "CDCEL937PWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cdcel937.pdf",+ "parts": {+ "symbol": "cdcel937pwr.kicad_sym",+ "footprint": "cdcel937pwr.kicad_mod",+ "model_3d": "cdcel937pwr-hero.glb",+ "model_3d_plain": "cdcel937pwr.glb",+ "model_3d_step": "cdcel937pwr-etched.step",+ "model_3d_step_plain": "cdcel937pwr.step",+ "lbr": "cdcel937pwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2662666",+ "digikey": "296-51008-2-ND",+ "mouser": "595-CDCEL937PWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:56:39Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-51008-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-CDCEL937PWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "Xin/CLK",+ "type": "input",+ "description": "Crystal oscillator input or LVCMOS clock input, selectable through the SDA/SCL bus."+ },+ {+ "number": "2",+ "name": "S0",+ "type": "input",+ "description": "User-programmable LVCMOS control input S0 with internal 500k pullup; in default mode it switches all outputs ON or OFF."+ },+ {+ "number": "3",+ "name": "VDD",+ "type": "power_in",+ "description": "1.8V power supply for the device."+ },+ {+ "number": "4",+ "name": "VCtrl",+ "type": "input",+ "description": "VCXO control voltage input; leave open or pull up (approximately 500k) when not used."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "6",+ "name": "Vddout",+ "type": "power_in",+ "description": "Output supply for all outputs; 1.8V for CDCEL937 (this pin is one of three Vddout pins, 6, 10 and 13)."+ },+ {+ "number": "7",+ "name": "Y4",+ "type": "output",+ "description": "LVCMOS output Y4."+ },+ {+ "number": "8",+ "name": "Y5",+ "type": "output",+ "description": "LVCMOS output Y5."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "10",+ "name": "Vddout",+ "type": "power_in",+ "description": "Output supply for all outputs; 1.8V for CDCEL937 (one of three Vddout pins, 6, 10 and 13)."+ },+ {+ "number": "11",+ "name": "Y7",+ "type": "output",+ "description": "LVCMOS output Y7."+ },+ {+ "number": "12",+ "name": "Y6",+ "type": "output",+ "description": "LVCMOS output Y6."+ },+ {+ "number": "13",+ "name": "Vddout",+ "type": "power_in",+ "description": "Output supply for all outputs; 1.8V for CDCEL937 (one of three Vddout pins, 6, 10 and 13)."+ },+ {+ "number": "14",+ "name": "Y3",+ "type": "output",+ "description": "LVCMOS output Y3."+ },+ {+ "number": "15",+ "name": "Y2",+ "type": "output",+ "description": "LVCMOS output Y2."+ },+ {+ "number": "16",+ "name": "GND",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "17",+ "name": "Y1",+ "type": "output",+ "description": "LVCMOS output Y1; its state (power down, 3-state, low or active) is user-definable in the Generic Configuration Register."+ },+ {+ "number": "18",+ "name": "SCL/S2",+ "type": "bidirectional",+ "description": "Serial clock input SCL in default configuration (LVCMOS, internal 500k pullup); can be reprogrammed as user control input S2."+ },+ {+ "number": "19",+ "name": "SDA/S1",+ "type": "bidirectional",+ "description": "Bidirectional serial data SDA in default configuration (LVCMOS, internal 500k pullup); can be reprogrammed as user control input S1."+ },+ {+ "number": "20",+ "name": "Xout",+ "type": "output",+ "description": "Crystal oscillator output; leave open or pull up (approximately 500k) when not used."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout taken from the PW (TSSOP-20) pin table on page 3; the orderable addendum (page 31) lists CDCE; Pins 18 (SCL/S2) and 19 (SDA/S1) are dual-function; they are typed bidirectional here because the de; Pin descriptions for Y4, Y5, Y6, Y7, Y2, Y3 are limited to the datasheet's 'LVCMOS outputs' label; t"+ ],+ "pages_sent": 11,+ "cost_usd": 0.0713,+ "at": "2026-10-08T15:56:20"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cdcel937.pdf",+ "pages": 39,+ "sha256": "c538114a66321dcf",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdcel937pwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdcel937pwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ba80efebe727352844a9bfcd23241aca79f2315b07b710b5ce8837f38d135127",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}