component
CDCEL913IPWRQ1
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
CDCEL913IPWRQ1
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-14
CDCEL913IPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Xin/CLK | input | Crystal oscillator input or LVCMOS clock input, selectable through the I2C bus. |
| 2 | S0 | input | User-programmable LVCMOS control input S0 with a 500-kΩ internal pullup; S0 is a control pin only and is not multi-use. |
| 3 | VDD | power_in | 1.8-V power supply for the device (recommended 1.7 V to 1.9 V). |
| 4 | Vctr | input | VCXO control voltage input; leave open or pull up when not used. |
| 5 | GND | power_in | Ground. |
| 6 | VDDOUT | power_in | For CDCEL913-Q1, 1.8-V supply for all outputs (recommended 1.7 V to 1.9 V). |
| 7 | VDDOUT | power_in | For CDCEL913-Q1, 1.8-V supply for all outputs (recommended 1.7 V to 1.9 V). |
| 8 | Y3 | output | LVCMOS output; output current limited to ±8 mA at VDDOUT = 1.8 V with 15-pF maximum load. |
| 9 | Y2 | output | LVCMOS output; output current limited to ±8 mA at VDDOUT = 1.8 V with 15-pF maximum load. |
| 10 | GND | power_in | Ground. |
| 11 | Y1 | output | LVCMOS output; output current limited to ±8 mA at VDDOUT = 1.8 V with 15-pF maximum load. |
| 12 | SCL/S2 | input | Serial clock input SCL (default, with 500-kΩ internal pullup) or user-programmable LVCMOS control input S2 (500-kΩ internal pullup) when reconfigured in EEPROM. |
| 13 | SDA/S1 | bidirectional | Bidirectional serial data SDA (default, LVCMOS internal pullup) or user-programmable LVCMOS control input S1 (500-kΩ internal pullup) when reconfigured in EEPROM. |
| 14 | Xout | output | Crystal oscillator output; leave open or pull up when not used. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Clock/Timing |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CDCEL913IPWRQ1 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cdcel913ipwrq1-etched.step/cdcel913ipwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdcel913ipwrq1.step/cdcel913ipwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
c15d74c946ff4223, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CDCEL913IPWRQ1
**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-14
CDCEL913IPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Xin/CLK | input | Crystal oscillator input or LVCMOS clock input, selectable through the I2C bus. |
| 2 | S0 | input | User-programmable LVCMOS control input S0 with a 500-kΩ internal pullup; S0 is a control pin only and is not multi-use. |
| 3 | VDD | power_in | 1.8-V power supply for the device (recommended 1.7 V to 1.9 V). |
| 4 | Vctr | input | VCXO control voltage input; leave open or pull up when not used. |
| 5 | GND | power_in | Ground. |
| 6 | VDDOUT | power_in | For CDCEL913-Q1, 1.8-V supply for all outputs (recommended 1.7 V to 1.9 V). |
| 7 | VDDOUT | power_in | For CDCEL913-Q1, 1.8-V supply for all outputs (recommended 1.7 V to 1.9 V). |
| 8 | Y3 | output | LVCMOS output; output current limited to ±8 mA at VDDOUT = 1.8 V with 15-pF maximum load. |
| 9 | Y2 | output | LVCMOS output; output current limited to ±8 mA at VDDOUT = 1.8 V with 15-pF maximum load. |
| 10 | GND | power_in | Ground. |
| 11 | Y1 | output | LVCMOS output; output current limited to ±8 mA at VDDOUT = 1.8 V with 15-pF maximum load. |
| 12 | SCL/S2 | input | Serial clock input SCL (default, with 500-kΩ internal pullup) or user-programmable LVCMOS control input S2 (500-kΩ internal pullup) when reconfigured in EEPROM. |
| 13 | SDA/S1 | bidirectional | Bidirectional serial data SDA (default, LVCMOS internal pullup) or user-programmable LVCMOS control input S1 (500-kΩ internal pullup) when reconfigured in EEPROM. |
| 14 | Xout | output | Crystal oscillator output; leave open or pull up when not used. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Clock/Timing |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `CDCEL913IPWRQ1`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cdcel913ipwrq1-etched.step` / `cdcel913ipwrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdcel913ipwrq1.step` / `cdcel913ipwrq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdcel913-q1) (39 pp, sha256 `c15d74c946ff4223`, retrieved 2026-10-11, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cdcel913ipwrq1-datasheet.pdf)