# CDCE925PWR

**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-16

CDCE925PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Xin/CLK | input | Crystal oscillator input or LVCMOS clock input (selectable through SDA/SCL bus). Accepts fundamental-mode crystal 8-32MHz or single-ended LVCMOS up to 160MHz. |
| 2 | S0 | input | User-programmable control input S0; LVCMOS input with internal pullup. Used for functions such as SSC selection, frequency switching, output enable, or power down. |
| 3 | VDD | power_in | 1.8V power supply for the device core (nominal 1.8V, range 1.7-1.9V). |
| 4 | VCtrl | input | VCXO control voltage input (0 to VDD). Leave open or pull up when not used. Provides frequency pulling for the on-chip VCXO (±150ppm typical). |
| 5 | GND | power_in | Device ground. |
| 6 | VDDOUT | power_in | Output supply voltage for the LVCMOS output drivers. CDCE925: 2.5V or 3.3V. CDCEL925: 1.8V. Separate from device core VDD to allow independent output level selection. |
| 7 | Y4 | output | LVCMOS clock output Y4. Drive levels set by VDDOUT (1.8V/2.5V/3.3V). Frequency programmable via SDA/SCL up to 230MHz. |
| 8 | Y5 | output | LVCMOS clock output Y5. Drive levels set by VDDOUT (1.8V/2.5V/3.3V). Frequency programmable via SDA/SCL up to 230MHz. |
| 9 | VDDOUT | power_in | Output supply voltage for the LVCMOS output drivers (second VDDOUT pin). CDCE925: 2.5V or 3.3V. CDCEL925: 1.8V. |
| 10 | Y3 | output | LVCMOS clock output Y3. Drive levels set by VDDOUT. Frequency programmable via SDA/SCL up to 230MHz. |
| 11 | Y2 | output | LVCMOS clock output Y2. Drive levels set by VDDOUT. Frequency programmable via SDA/SCL up to 230MHz. |
| 12 | GND | power_in | Device ground. |
| 13 | Y1 | output | LVCMOS clock output Y1. Drive levels set by VDDOUT. Frequency programmable via SDA/SCL up to 230MHz. |
| 14 | SCL/S2 | input | SCL: Serial clock input in the default configuration (2-wire SDA/SCL bus for register/EEPROM programming), LVCMOS with internal pullup. Alternate function S2: user-programmable control input (LVCMOS, internal pullup). |
| 15 | SDA/S1 | bidirectional | SDA: Bidirectional serial data input/output in the default configuration (2-wire SDA/SCL bus), LVCMOS with internal pullup. Alternate function S1: user-programmable control input (LVCMOS, internal pullup). |
| 16 | Xout | output | Crystal oscillator output. Leave open or pull up when not used (e.g., when driving Xin/CLK with an LVCMOS clock). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Clock/Timing |
| Pins | 16 |

## Ordering variants

Same part, different packaging or reel option.

- `CDCE925PWR`

## CAD (KiCad official)

- Symbol: `CDCE925PWR`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `cdce925pwr-etched.step` / `cdce925pwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdce925pwr.step` / `cdce925pwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cdce925.pdf) (39 pp, sha256 `8cad0c8b46232d03`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cdce925pwr-datasheet.pdf)