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CDCE913PWR

Public Made by Adom

by adom

Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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docs cdce913pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cdce913pwr: viewers · Ray
cdce913pwr-etched.fit.json cdce913pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cdce913pwr-etched.glb cdce913pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cdce913pwr-etched.step cdce913pwr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cdce913pwr.glb Publish 0.1.0 · Ray
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cdce913pwr.step Publish 0.1.0 · Ray
package.json cdce913pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
page.json cdce913pwr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
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CDCE913PWR

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-14

CDCE913PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Xin/CLK input Crystal oscillator input or LVCMOS clock input (selectable through SDA/SCL bus); 8-160 MHz input frequency range.
2 S0 input User-programmable control input S0; LVCMOS inputs; 500-kΩ internal pullup; input voltage range 0-1.9 V.
3 VDD power_in 1.8-V power supply for the device; recommended operating voltage 1.7-1.9 V.
4 VCtrl input VCXO control voltage input for on-chip VCXO; leave open or pull up when not used; voltage range 0-VDD.
5 GND power_in Ground.
6 VDDOUT power_out 3.3-V or 2.5-V supply for all outputs (CDCE913); recommended output voltage range 2.3-3.6 V.
7 VDDOUT power_out 3.3-V or 2.5-V supply for all outputs (CDCE913); recommended output voltage range 2.3-3.6 V.
8 Y3 output LVCMOS output clock; programmable frequency up to 230 MHz; output current ±12 mA @ 3.3 V, ±10 mA @ 2.5 V.
9 Y2 output LVCMOS output clock; programmable frequency up to 230 MHz; output current ±12 mA @ 3.3 V, ±10 mA @ 2.5 V.
10 GND power_in Ground.
11 Y1 output LVCMOS output clock; programmable frequency up to 230 MHz; output current ±12 mA @ 3.3 V, ±10 mA @ 2.5 V.
12 SCL/S2 input SCL: serial clock input LVCMOS (default configuration) with 500-kΩ internal pullup; or S2: user-programmable control input; input voltage range 0-3.6 V.
13 SDA/S1 bidirectional SDA: bidirectional serial data input/output (default configuration) with LVCMOS internal pullup; or S1: user-programmable control input; voltage range 0-3.6 V.
14 Xout output Crystal oscillator output; leave open or pull up when not used; output voltage 0-VDD.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Clock/Timing
Pins 14

CAD (KiCad official)

  • Symbol: CDCE913PWR
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cdce913pwr-etched.step / cdce913pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce913pwr.step / cdce913pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 6d60c6c29b56ed67, retrieved 2026-09-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF