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CDCE913PW

Public Made by Adom

by adom

Texas Instruments Clock Generators / Frequency Synthesizers / PLL, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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CDCE913PW

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · TSSOP-14

CDCE913PW from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Xin/CLK input Crystal oscillator input or LVCMOS clock input, selectable through the SDA/SCL bus; the CLK input voltage range is 0 V to 1.9 V.
2 S0 input User-programmable LVCMOS control input with a 500-kΩ internal pullup; the S0 input voltage range is 0 V to 1.9 V, and S0 is a control pin only.
3 VDD power_in 1.8-V device power supply, with a recommended range of 1.7 V to 1.9 V.
4 VCtrl input VCXO control voltage input; leave open or pull up when not used, with a frequency control voltage range of 0 V to VDD.
5 GND power_in Ground.
6 VDDOUT power_in Output supply for all outputs; 3.3 V or 2.5 V for CDCE913 (recommended VDDOUT range 2.3 V to 3.6 V).
7 VDDOUT power_in Output supply for all outputs; 3.3 V or 2.5 V for CDCE913 (recommended VDDOUT range 2.3 V to 3.6 V).
8 Y3 output LVCMOS clock output Y3, with output current limited to ±12 mA at VDDOUT = 3.3 V, ±10 mA at 2.5 V, and ±8 mA at 1.8 V.
9 Y2 output LVCMOS clock output Y2, with output current limited to ±12 mA at VDDOUT = 3.3 V, ±10 mA at 2.5 V, and ±8 mA at 1.8 V.
10 GND power_in Ground.
11 Y1 output LVCMOS clock output Y1, with output current limited to ±12 mA at VDDOUT = 3.3 V, ±10 mA at 2.5 V, and ±8 mA at 1.8 V.
12 SCL/S2 input Serial clock input (SCL, LVCMOS, default function) with 500-kΩ internal pullup, or user-programmable control input S2 with 500-kΩ internal pullup when reconfigured in EEPROM; SCL/S2 input voltage range is 0 V to 3.6 V.
13 SDA/S1 bidirectional Bidirectional serial data pin (SDA, default function) with internal pullup, or user-programmable control input S1 with 500-kΩ internal pullup when reconfigured in EEPROM; SDA/S1 input voltage range is 0 V to 3.6 V.
14 Xout output Crystal oscillator output; leave open or pull up when not used.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-14
Category Clock and Timing
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD supply voltage VDD -0.5 2.5 V 4
VDDOUT output clocks supply voltage (CDCE913) VDDOUT -0.5 V 4
Input voltage VI -0.5 V 4
Output voltage VO -0.5 V 4
Input current II 20 mA VI < 0, VI > VDD 4
Continuous output current IO 50 mA 4
Maximum junction temperature TJ 125 °C 4
Storage temperature Tstg -65 150 °C 4
Device supply voltage VDD 1.7 1.8 1.9 V 4
Output Yx supply voltage for CDCE913, VDDOUT VO 2.3 3.6 V 4
Input voltage range S0 VI(S) 0 1.9 V 4
Input voltage range S1, S2, SDA, SCL VI(S) 0 3.6 V VI(thresh) = 0.5 VDD 4
Input voltage range CLK VI(CLK) 0 1.9 V 4
Output current IOH/IOL -12 12 mA VDDOUT = 3.3 V 4
Output current IOH/IOL -10 10 mA VDDOUT = 2.5 V 4
Output load, LVCMOS CL 15 pF 4
Operating free-air temperature TA -40 85 °C 4
Crystal input frequency range (fundamental mode) fXtal 8 27 32 MHz fundamental mode 4
Pulling range fPR -120 150 ppm 0 V ≤ VCtrl ≤ 1.8 V 4
Frequency control voltage VCtrl 0 V 4
On-chip load capacitance at Xin and Xout CL 0 20 pF 5
Supply voltage Vdd threshold for power-up control circuit V(PUC) 0.85 1.45 V 5
VCO frequency range of PLL fVCO 80 230 MHz 5
LVCMOS input current II -5 5 μA VI = 0 V or VDD; VDD = 1.9 V 5
SCL and SDA input current IIH -10 10 μA VI = VDD; VDD = 1.9 V 6
Input capacitance at SCL/SDA CI 3 10 pF VI = 0 V or VDD 7
Output duty cycle (VDDOUT = 3.3 V mode) odc 45 55 % fVCO = 100 MHz; Pdiv = 1 6
Output duty cycle (VDDOUT = 2.5 V mode) odc 45 55 % fVCO = 100 MHz; Pdiv = 1 6
Cycle-to-cycle jitter (VDDOUT = 3.3 V mode) tjit(cc) 50 70 ps 1 PLL switching, Y2-to-Y3 6
Peak-to-peak period jitter (VDDOUT = 3.3 V mode) tjit(per) 60 100 ps 1 PLL switching, Y2-to-Y3 6
Cycle-to-cycle jitter (VDDOUT = 2.5 V mode) tjit(cc) 50 70 ps 1 PLL switching, Y2-to-Y3 6
Peak-to-peak period jitter (VDDOUT = 2.5 V mode) tjit(per) 60 100 ps 1 PLL switching, Y2-to-Y3 6
LVCMOS clock input frequency, PLL bypass mode fCLK 0 160 MHz PLL bypass mode 7
LVCMOS clock input frequency, PLL mode fCLK 8 160 MHz PLL mode 7
Duty cycle CLK 40 60 % at VDD/2 7
SCL clock frequency fSCL 0 100 kHz Standard mode 7
SCL clock frequency fSCL 0 400 kHz Fast mode 7
SDA hold time (SDA valid after SCL low) th(SDA) 0 3.45 μs Standard mode 7
SDA hold time (SDA valid after SCL low) th(SDA) 0 0.9 μs Fast mode 7
SCL/SDA input rise time tr 1000 ns Standard mode 7
SCL/SDA input rise time tr 300 ns Fast mode 7
START setup time (SCL high before SDA low) tsu(START) 4.7 μs Standard mode 7
START setup time (SCL high before SDA low) tsu(START) 0.6 μs Fast mode 7
START hold time (SCL low after SDA low) th(START) 4 μs Standard mode 7
START hold time (SCL low after SDA low) th(START) 0.6 μs Fast mode 7
SCL low-pulse duration tw(SCLL) 4.7 μs Standard mode 7
SCL low-pulse duration tw(SCLL) 1.3 μs Fast mode 7
SCL high-pulse duration tw(SCLH) 4 μs Standard mode 7
SCL high-pulse duration tw(SCLH) 0.6 μs Fast mode 7
STOP setup time tsu(STOP) 4 μs Standard mode 7
STOP setup time tsu(STOP) 0.6 μs Fast mode 7
Junction-to-ambient thermal resistance RθJA 106 °C/W Airflow 0 lfm 5
Junction-to-ambient thermal resistance RθJA 93 °C/W Airflow 150 lfm 5
Junction-to-ambient thermal resistance RθJA 92 °C/W Airflow 200 lfm 5
Junction-to-ambient thermal resistance RθJA 90 °C/W Airflow 250 lfm 5
Junction-to-ambient thermal resistance RθJA 85 °C/W Airflow 500 lfm 5
Junction-to-case (top) thermal resistance RθJC(top) 1.4 °C/W 5
Junction-to-board thermal resistance RθJB 66 °C/W 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 62 °C/W 5

CAD (KiCad official)

  • Symbol: CDCE913PW
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: cdce913pw-etched.step / cdce913pw-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce913pw.step / cdce913pw.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 6d60c6c29b56ed67, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF