component

CDCE906PWR

Public Made by Adom

by adom

Texas Instruments Clock Generators / Frequency Synthesizers / PLL, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcdce906pwrfactory-2.0.0extractor-text

Verified CDCE906PWR

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 20 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCE906PWR · TSSOP-20 · 20 pins
  • ✓copper: 20 copper pads, none touching another net
  • ✓datasheet: all 20 pin names found in the 46-page datasheet
  • ✓distributor: lcsc C2663663, digikey 296-26038-2-ND, mouser 595-CDCE906PWR
  • ✓family: TSSOP-20_4.4x6.5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ubyig9we/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 20 pins = 20 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 20 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdce906pwr.kicad_sym✓ cdce906pwr.kicad_mod✓ cdce906pwr.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cdce906pwr: viewers · Ray
cdce906pwr-etched.glb Publish 0.1.0 · Ray
cdce906pwr-etched.step cdce906pwr: factory component page (tier=mfr) · Ray
cdce906pwr-hero.glb cdce906pwr: hero GLB from the etched model (keeps the MPN mark) · Ray
cdce906pwr-hero.overlay.json Publish 0.1.0 · Ray
cdce906pwr.glb Publish 0.1.0 · Ray
cdce906pwr.kicad_mod Publish 0.1.0 · Ray
cdce906pwr.kicad_sym Publish 0.1.0 · Ray
cdce906pwr.lbr Publish 0.1.0 · Ray
cdce906pwr.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 20 pins · Ray

CDCE906PWR

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · TSSOP-20

CDCE906PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S0/A0/CLK_SEL input User programmable control input S0 (PLL bypass or power-down), address bit A0, or CLK_SEL (selects one of two LVCMOS clock inputs) depending on SMBus settings; LVCMOS input with internal 150 kΩ pullup.
2 S1/A1 input User programmable control input S1 (output enable/disable or all outputs low) or address bit A1 depending on SMBus settings; LVCMOS input with internal 150 kΩ pullup.
3 VCC power_in 3.3-V device power supply, specified from 3 V minimum to 3.6 V maximum.
4 GND power_in Ground.
5 CLK_IN0 input Crystal oscillator input, or LVCMOS input, or positive differential signal input depending on SMBus settings; PLL mode input frequency 1 to 167 MHz.
6 CLK_IN1 bidirectional Crystal oscillator output, or second LVCMOS input, or negative differential signal input depending on SMBus settings.
7 VCC power_in 3.3-V device power supply, specified from 3 V minimum to 3.6 V maximum.
8 GND power_in Ground.
9 SDATA bidirectional Serial control data input/output for the SMBus controller; LVCMOS input.
10 SCLOCK input Serial control clock input for the SMBus controller; LVCMOS input with SCLK frequency up to 100 kHz.
11 Y0 output LVCMOS output powered from VCCOUT1 (2.3 V to 3.6 V); output frequencies up to 167 MHz.
12 Y1 output LVCMOS output powered from VCCOUT1 (2.3 V to 3.6 V); output frequencies up to 167 MHz.
13 GND power_in Ground.
14 VCCOUT1 power_in Power supply for outputs Y0 and Y1, specified from 2.3 V to 3.6 V.
15 Y2 output LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); output frequencies up to 167 MHz.
16 Y3 output LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); output frequencies up to 167 MHz.
17 GND power_in Ground.
18 VCCOUT2 power_in Power supply for outputs Y2, Y3, Y4 and Y5, specified from 2.3 V to 3.6 V.
19 Y4 output LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); output frequencies up to 167 MHz.
20 Y5 output LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); output frequencies up to 167 MHz.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-20
Category RTC/Clock Chip
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 4.6 V absolute maximum supply voltage range 4
Device supply voltage VCC 3 3.3 3.6 V recommended operating 5
Output Y0,Y1 supply voltage VCCOUT1 2.3 3.6 V recommended operating 5
Output Y2,Y3,Y4,Y5 supply voltage VCCOUT2 2.3 3.6 V recommended operating 5
Operating free-air temperature TA 0 70 °C recommended operating 5
Input current (VI<0, VI>VCC) II -20 20 mA absolute maximum 4
Continuous output current IO -50 50 mA absolute maximum 4
Storage temperature range Tstg -65 150 °C absolute maximum 4
Maximum junction temperature TJ 125 °C absolute maximum 4
Input voltage range VI -0.5 V max VCC + 0.5 as printed 4
Output voltage range VO -0.5 V max VCC + 0.5 as printed 4
Thermal resistance junction-to-ambient θJA 66.3 °C/W 0 LFM airflow, TSSOP20 (PW) 4
Thermal resistance junction-to-ambient θJA 59.3 °C/W 150 LFM airflow, TSSOP20 (PW) 4
Thermal resistance junction-to-ambient θJA 56.3 °C/W 250 LFM airflow, TSSOP20 (PW) 4
Thermal resistance junction-to-ambient θJA 51.9 °C/W 500 LFM airflow, TSSOP20 (PW) 4
Thermal resistance junction-to-case θJC 19.7 °C/W TSSOP20 (PW) 4
Crystal input frequency range (fundamental mode) fXtal 8 27 54 MHz crystal specifications 5
Effective series resistance ESR 60 Ω crystal specifications; printed values 15 and 60 with column not clearly assigned 5
Input capacitance CLK_IN0 and CLK_IN1 CIN 3 pF crystal specifications 5
CLK_IN clock input frequency PLL mode fCLK_IN 1 167 MHz PLL mode, LVCMOS or differential 5
CLK_IN clock input frequency PLL bypass mode fCLK_IN 0 167 MHz PLL bypass mode, LVCMOS or differential 5
Rise and fall time CLK_IN signal tr/tf 4 ns 20% to 80% 5
Duty cycle CLK_IN dutyREF 40 60 % CLK_IN at VCC/2 5
Programming cycles of EEPROM EEcyc 100 1000 Cycles EEPROM specification; printed MIN TYP MAX columns with two values 5
Data retention EEret 10 Years EEPROM specification 5
SCLK frequency fSCLK 100 kHz SMBus timing requirements 5
START hold time th(START) 4 µs SMBus timing requirements 5
SCLK low-pulse duration tw(SCLL) 4.7 µs SMBus timing requirements 5
SCLK high-pulse duration tw(SCLH) 4 50 µs SMBus timing requirements 5
START setup time tsu(START) 0.6 µs SMBus timing requirements 5
SDATA hold time th(SDATA) 0.3 µs SMBus timing requirements 5
SDATA setup time tsu(SDATA) 0.25 µs SMBus timing requirements 5
SCLK / SDATA input rise time tr 1000 ns SMBus timing requirements 5
SCLK / SDATA input fall time tf 300 ns SMBus timing requirements 5
STOP setup time tsu(STOP) 4 µs timing requirements 6
Bus free time tBUS 4.7 µs timing requirements 6
Time in which the device must be operational after power-on reset tPOR 500 ms timing requirements 6
Supply current ICC 90 115 mA All PLLs on, all outputs on, fout = 80 MHz, fCLK_IN = 27 MHz, fvco = 160 MHz 6
Power down current ICCPD 50 µA fIN = 0 MHz, VCC = 3.6 V, every circuit powered down except SMBus 6
Supply voltage Vcc threshold for power up control circuit VPUC 2.1 V 6
VCO frequency of internal PLL normal speed-mode fVCO 80 200 MHz All PLLs, normal speed-mode 6
VCO frequency of internal PLL high-speed mode fVCO 180 300 MHz All PLLs, high-speed mode 6
VCO frequency PLL2 with SSC fVCO 80 167 MHz PLL2 with SSC 6
LVCMOS output frequency range fOUT 167 MHz VCC = 2.5 V or 3.3 V 6
LVCMOS input voltage clamp VIK -1.2 V VCC = 3 V, II = -18 mA 6
LVCMOS input current CLK_IN0 / CLK_IN1 II -5 5 µA VI = 0 V or VCC, VCC = 3.6 V 6
LVCMOS input current high (S1/S0) IIH 5 µA VI = VCC, VCC = 3.6 V 6
LVCMOS input current low (S1/S0) IIL -35 -10 µA VI = 0 V, VCC = 3.6 V 6
Input capacitance at CLK_IN0 and CLK_IN1 CI 3 pF VI = 0 V or VCC 6
LVCMOS high-level output voltage (Vccout = 3.3 V mode) VOH 2.9 V Vccout = 3 V, IOH = -0.1 mA 6
LVCMOS high-level output voltage (Vccout = 3.3 V mode) VOH 2.4 V Vccout = 3 V, IOH = -4 mA 6
LVCMOS high-level output voltage (Vccout = 3.3 V mode) VOH 2.1 V Vccout = 3 V, IOH = -6 mA 6
LVCMOS low-level output voltage (Vccout = 3.3 V mode) VOL 0.1 V Vccout = 3 V, IOL = 0.1 mA 6
LVCMOS low-level output voltage (Vccout = 3.3 V mode) VOL 0.5 V Vccout = 3 V, IOL = 4 mA 6
LVCMOS low-level output voltage (Vccout = 3.3 V mode) VOL 0.85 V Vccout = 3 V, IOL = 6 mA 6
Rise and fall time output slew rate 0 tr0/tf0 1.7 3.3 4.8 ns Vccout = 3.3 V (20%-80%) 6
Rise and fall time output slew rate 1 tr1/tf1 1.5 2.5 3.2 ns Vccout = 3.3 V (20%-80%) 6
Rise and fall time output slew rate 2 tr2/tf2 1.2 1.6 2.1 ns Vccout = 3.3 V (20%-80%) 6
Rise and fall time output slew rate 3 (default) tr3/tf3 0.4 0.6 1 ns Vccout = 3.3 V (20%-80%) 6
Propagation delay tPLH/tPHL 9 ns All PLL bypass 6
Propagation delay tPLH/tPHL 11 ns VCO bypass 6
Cycle-to-cycle jitter 1 PLL 1 output tjit(cc) 65 95 ps fOUT = 24.576 MHz, 50000 cycles 7
Cycle-to-cycle jitter 3 PLLs 3 outputs tjit(cc) 85 135 ps fOUT = 24.576 MHz, 50000 cycles 7
Peak-to-peak period jitter 1 PLL 1 output tjit(per) 90 115 ps fOUT = 24.576 MHz 7
Peak-to-peak period jitter 3 PLLs 3 outputs tjit(per) 100 150 ps fOUT = 24.576 MHz 7
Output skew 1.6-ns rise/fall time tsk(o) 200 ps fVCO = 150 MHz, Pdiv = 3 7
Output duty cycle odc 45 55 % fVCO = 100 MHz, Pdiv = 1 7
LVCMOS high-level output voltage (Vccout = 2.5 V mode) VOH 2.2 V Vccout = 2.3 V, IOH = 0.1 mA 7
LVCMOS high-level output voltage (Vccout = 2.5 V mode) VOH 1.7 V Vccout = 2.3 V, IOH = -3 mA 7
LVCMOS high-level output voltage (Vccout = 2.5 V mode) VOH 1.5 V Vccout = 2.3 V, IOH = -4 mA 7
LVCMOS low-level output voltage (Vccout = 2.5 V mode) VOL 0.1 V Vccout = 2.3 V, IOL = 0.1 mA 7
LVCMOS low-level output voltage (Vccout = 2.5 V mode) VOL 0.5 V Vccout = 2.3 V, IOL = 3 mA 7
LVCMOS low-level output voltage (Vccout = 2.5 V mode) VOL 0.85 V Vccout = 2.3 V, IOL = 4 mA 7
SCLK input high voltage VIH 2.1 V SMBus 7
SCLK input low voltage VIL 0.8 V SMBus 7
SDATA low-level output voltage VOL 0.4 V IOL = 4 mA, VCC = 3 V 7

CAD (KiCad official)

  • Symbol: CDCE906PWR
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: cdce906pwr-etched.step / cdce906pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce906pwr.step / cdce906pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 21c27c6728cc3d60, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF