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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

CDCE72010RGCT

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-64-EP(9x9)

CDCE72010RGCT from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TESTOUTA	passive	Analog test point for TI internal testing; connect a 1kΩ pull-down resistor or leave unconnected.
2	GND_CP	power_in	Analog ground for the charge pump.
3	CP_OUT	output	Charge pump output.
4	VCC_PLL	power_in	3.3V PLL supply voltage for the PLL circuitry; internally connected to pin 63.
5	VCC	power_in	3.3V supply for the output buffers; internally connected to pin 8.
6	U0N	output	Negative output 0, user definable as LVPECL, LVDS or LVCMOS via SPI.
7	U0P	output	Positive output 0, user definable as LVPECL, LVDS or LVCMOS via SPI.
8	VCC	power_in	3.3V supply for the output buffers; internally connected to pin 5.
9	U1N	output	Negative output 1, user definable as LVPECL, LVDS or LVCMOS via SPI.
10	U1P	output	Positive output 1, user definable as LVPECL, LVDS or LVCMOS via SPI.
11	VCC	power_in	3.3V supply for the output buffers.
12	U2N	output	Negative output 2, user definable as LVPECL, LVDS or LVCMOS via SPI.
13	U2P	output	Positive output 2, user definable as LVPECL, LVDS or LVCMOS via SPI.
14	VCC	power_in	3.3V supply for the output buffers.
15	SPI_MISO	tri_state	3-state LVCMOS serial data output to the SPI bus, enabled when SPI_LE is asserted low.
16	MODE_SEL	input	High or unconnected selects SPI mode; tied low selects configuration default (CD) mode, loading defaults from EEPROM at start-up.
17	PD	input	Active-low power-down input (or SPI bit) with internal 150-kΩ pull-up, defaulting to logic 1 if unconnected.
18	AUX_SEL	input	CD-mode only: 1 or unconnected disables output 9 and enables the auxiliary input to drive outputs 0 to 8; low enables output 9 with outputs driven by the VCXO input.
19	VCC	power_in	3.3V supply for the output buffers.
20	U3N	output	Negative output 3, user definable as LVPECL, LVDS or LVCMOS via SPI.
21	U3P	output	Positive output 3, user definable as LVPECL, LVDS or LVCMOS via SPI.
22	VCC	power_in	3.3V supply for the output buffers.
23	U4N	output	Negative output 4, user definable as LVPECL, LVDS or LVCMOS via SPI.
24	U4P	output	Positive output 4, user definable as LVPECL, LVDS or LVCMOS via SPI.
25	VCC	power_in	3.3V supply for the output buffers.
26	U5N	output	Negative output 5, user definable as LVPECL, LVDS or LVCMOS via SPI.
27	U5P	output	Positive output 5, user definable as LVPECL, LVDS or LVCMOS via SPI.
28	VCC	power_in	3.3V supply for the output buffers; internally connected to pin 31.
29	U6N	output	Negative output 6, user definable as LVPECL, LVDS or LVCMOS via SPI.
30	U6P	output	Positive output 6, user definable as LVPECL, LVDS or LVCMOS via SPI.
31	VCC	power_in	3.3V supply for the output buffers; internally connected to pin 28.
32	GND	power_in	Ground, connected to the thermal pad internally.
33	RESET/HOLD	input	Active-low LVCMOS input programmable via SPI as RESET (default) or HOLD, with internal 150-kΩ pull-up; RESET 3-states the charge pump and resets counters, HOLD only 3-states the charge pump.
34	VCC	power_in	3.3V supply for the output buffers.
35	U7N	output	Negative output 7, user definable as LVPECL, LVDS or LVCMOS via SPI.
36	U7P	output	Positive output 7, user definable as LVPECL, LVDS or LVCMOS via SPI.
37	VCC	power_in	3.3V supply for the output buffers.
38	U8N	output	Negative output 8, user definable as LVPECL, LVDS or LVCMOS via SPI.
39	U8P	output	Positive output 8, user definable as LVPECL, LVDS or LVCMOS via SPI.
40	VCC	power_in	3.3V supply for the output buffers; internally connected to pin 43.
41	U9N/AUXINN	bidirectional	Negative universal output buffer 9 that can be 3-stated and used as negative auxiliary input buffer, requiring external termination.
42	U9P/AUXINP	bidirectional	Positive universal output buffer 9 that can be 3-stated and used as positive auxiliary input buffer, requiring external termination.
43	VCC	power_in	3.3V supply for the output buffers; internally connected to pin 40.
44	SPI_MOSI/CD3	input	LVCMOS serial control data input for the SPI bus; becomes CD3 in configuration default mode and should be tied to GND.
45	SPI_LE/CD1	input	LVCMOS control latch enable input for the SPI with hysteresis; becomes CD1 in configuration default mode.
46	SPI_CLK/CD2	input	LVCMOS serial control clock input for the SPI bus with hysteresis; becomes CD2 in configuration default mode.
47	REF_SEL	input	External reference select when auto select is off (1 = PRI_REF, 0 = SEC_REF), with internal 150-kΩ pull-up defaulting to logic 1.
48	VCCA	power_in	3.3V supply for internal analog circuitry.
49	VCCA	power_in	3.3V supply for internal analog circuitry.
50	PLL_LOCK	output	LVCMOS PLL lock indicator, high when the PLL is in lock, programmable as digital or analog lock detect.
51	VCC_VCXO	power_in	3.3V VCXO input buffer and circuitry supply; internally connected to pin 54.
52	VCXO_IN-	input	Complementary VCXO input for LVPECL/LVDS; for an LVCMOS input on VCXO_IN+, ground this pin through a 1k resistor.
53	VCXO_IN+	input	VCXO positive input for LVPECL, LVDS and LVCMOS level inputs.
54	VCC_VCXO	power_in	3.3V VCXO input buffer and circuitry supply; internally connected to pin 51.
55	STATUS	output	LVCMOS output for TI internal testing; leave unconnected unless configured as IREF_CP, then connect a 12-kΩ resistor to GND.
56	VBB	output	Internal voltage bias analog output.
57	VCC_IN	power_in	3.3V reference input buffers and circuitry supply; internally connected to pin 60.
58	PRI_REF-	input	Negative primary reference clock input (LVPECL, LVDS); for LVCMOS ground this pin through a 1k resistor.
59	PRI_REF+	input	Positive primary reference clock input (LVPECL, LVDS, LVCMOS).
60	VCC_IN	power_in	3.3V reference input buffers and circuitry supply; internally connected to pin 57.
61	SEC_REF-	input	Negative secondary reference clock input (LVPECL, LVDS); for LVCMOS ground this pin through a 1k resistor.
62	SEC_REF+	input	Positive secondary reference clock input (LVPECL, LVDS, LVCMOS).
63	VCC_PLL	power_in	3.3V PLL supply voltage for the PLL circuitry; internally connected to pin 4.
64	VCC_CP	power_in	Charge pump supply, same as the external VCO/VCXO supply, settable from 2.3V to 3.6V.
65	GND_PAD	power_in	Ground on the thermal pad; see layout recommendations.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-64-EP(9x9)
Category	Clock/Timing
Pins	65

CAD (KiCad official)

Symbol: CDCE72010RGCT
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: cdce72010rgct-etched.step / cdce72010rgct-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce72010rgct.step / cdce72010rgct.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (78 pp, sha256 125ed3ab5da2d5d2, retrieved 2026-10-10, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF