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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

CDCE706PWR

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · TSSOP-20

CDCE706PWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	S0/A0/CLK_SEL	input	User-programmable control input S0 (PLL bypass or power-down mode), address bit A0, or CLK_SEL (selects one of two LVCMOS clock inputs), depending on SMBus settings; LVCMOS input with internal 150 kΩ pullup.
2	S1/A1	input	User-programmable control input S1 (output enable/disable or all outputs low) or address bit A1, depending on SMBus settings; LVCMOS input with internal 150 kΩ pullup.
3	VCC	power_in	3.3-V device power supply; recommended range 3 V to 3.6 V.
4	GND	power_in	Ground.
5	CLK_IN0	input	Crystal oscillator input, or LVCMOS input, or positive differential input depending on SMBus settings; accepts crystals from 8 MHz to 54 MHz and LVCMOS or differential inputs up to 200 MHz.
6	CLK_IN1	bidirectional	Crystal oscillator output, or second LVCMOS input, or negative differential input depending on SMBus settings.
7	VCC	power_in	3.3-V device power supply; recommended range 3 V to 3.6 V.
8	GND	power_in	Ground.
9	SDATA	bidirectional	Serial control data input/output for the SMBus controller; LVCMOS input.
10	SCLOCK	input	Serial control clock input for the SMBus controller; LVCMOS input.
11	Y0	output	LVCMOS output powered from VCCOUT1 (2.3 V to 3.6 V); rated ±6 mA at 3.3 V or ±4 mA at 2.5 V into a 25 pF maximum load.
12	Y1	output	LVCMOS output powered from VCCOUT1 (2.3 V to 3.6 V); rated ±6 mA at 3.3 V or ±4 mA at 2.5 V into a 25 pF maximum load.
13	GND	power_in	Ground.
14	VCCOUT1	power_in	Power supply for outputs Y0 and Y1; 2.3 V to 3.6 V.
15	Y2	output	LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); rated ±6 mA at 3.3 V or ±4 mA at 2.5 V into a 25 pF maximum load.
16	Y3	output	LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); rated ±6 mA at 3.3 V or ±4 mA at 2.5 V into a 25 pF maximum load.
17	GND	power_in	Ground.
18	VCCOUT2	power_in	Power supply for outputs Y2, Y3, Y4 and Y5; 2.3 V to 3.6 V.
19	Y4	output	LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); rated ±6 mA at 3.3 V or ±4 mA at 2.5 V into a 25 pF maximum load.
20	Y5	output	LVCMOS output powered from VCCOUT2 (2.3 V to 3.6 V); rated ±6 mA at 3.3 V or ±4 mA at 2.5 V into a 25 pF maximum load.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-20
Category	Clock/Timing
Pins	20

CAD (KiCad official)

Symbol: CDCE706PWR
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: cdce706pwr-etched.step / cdce706pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce706pwr.step / cdce706pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (46 pp, sha256 ed7f2ff38041e7cf, retrieved 2026-10-08, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF