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CDCE6214TWRGERQ1

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by adom

Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CDCE6214TWRGERQ1

Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · QFN-24(4x4)

CDCE6214TWRGERQ1 from Texas Instruments, in a QFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SECREF_P input Secondary reference input accepts differential or single-ended clock or crystal input (XOUT for crystal) with AC coupling capacitor and configurable internal biasing based on input mode.
2 SECREF_N input Secondary reference input (differential pair, XIN for crystal) accepts differential or single-ended clock input with AC coupling capacitor and configurable internal biasing based on input mode.
3 VDD_REF power_in Power supply (1.8V, 2.5V, or 3.3V ±5%) for reference input circuits, digital core, and I2C pull-up resistors.
4 REFSEL input Reference input selection control pin (three-state) with 50kΩ pull-up and 50kΩ pull-down resistors for selecting primary or secondary reference source.
5 PRIREF_P input Primary reference input accepts differential or single-ended clock with AC coupling capacitor and configurable internal biasing based on input mode.
6 PRIREF_N input Primary reference input (differential pair) accepts differential or single-ended clock with AC coupling capacitor and configurable internal biasing based on input mode.
7 OUT0 output LVCMOS output 0 with programmable slew rate and reference input bypass capability to allow reference clock routing to output.
8 PDN input Power-down/reset input (active low) or synchronization signal input (SYNCN) with 50kΩ pull-up resistor (disabled in output mode).
9 OUT4_N output Negative output of differential pair 4 supporting LVDS, LP-HCSL, or LVCMOS output standards with programmable driver configuration.
10 OUT4_P output Positive output of differential pair 4 supporting LVDS, LP-HCSL, or LVCMOS output standards with programmable driver configuration.
11 GPIO4 bidirectional General purpose input/output pin that can function as PLL lock status output or GPIO input with programmable configuration.
12 SCL/GPIO3 input I2C serial clock input or GPIO3 input, requires external pull-up resistor to VDD_REF in I2C mode with fail-safe input capability.
13 OUT3_N output Negative output of differential pair 3 supporting LVDS or LP-HCSL output standards with programmable driver configuration.
14 OUT3_P output Positive output of differential pair 3 supporting LVDS or LP-HCSL output standards with programmable driver configuration.
15 VDDO_34 power_in Power supply (1.8V, 2.5V, or 3.3V ±5%) for OUT0, OUT3, and OUT4 output channels with independent voltage configuration.
16 VDDO_12 power_in Power supply (1.8V, 2.5V, or 3.3V ±5%) for OUT1 and OUT2 output channels with independent voltage configuration.
17 OUT2_N output Negative output of differential pair 2 supporting LVDS or LP-HCSL output standards with programmable driver configuration.
18 OUT2_P output Positive output of differential pair 2 supporting LVDS or LP-HCSL output standards with programmable driver configuration.
19 SDA/GPIO2 bidirectional I2C serial data open-drain bidirectional output or GPIO2 input, requires external pull-up resistor to VDD_REF in I2C mode with fail-safe input.
20 GPIO1 bidirectional General purpose input/output pin that can function as PLL lock status output or GPIO input with programmable configuration.
21 OUT1_N output Negative output of differential pair 1 supporting LVDS, LP-HCSL, or LVCMOS output standards with programmable driver configuration.
22 OUT1_P output Positive output of differential pair 1 supporting LVDS, LP-HCSL, or LVCMOS output standards with programmable driver configuration.
23 HW_SW_CTRL input EEPROM page selection control pin (three-state) with 50kΩ pull-up and 50kΩ pull-down resistors for selecting factory or user-programmed configuration page.
24 VDD_VCO power_in Power supply (1.8V, 2.5V, or 3.3V ±5%) for PLL, VCO, and charge pump circuits.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package QFN-24(4x4)
Category Clock/Timing
Pins 25

CAD (KiCad official)

  • Symbol: CDCE6214TWRGERQ1
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: QFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: cdce6214twrgerq1-etched.step / cdce6214twrgerq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce6214twrgerq1.step / cdce6214twrgerq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (60 pp, sha256 5f5e24f0443f0c03, retrieved 2026-09-22, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF