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CDCE6214RGET
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+62@@ -0,0 +1,62 @@+# CDCE6214RGET++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · VQFN-24(4x4)++CDCE6214RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SECREF_P | input | Secondary external clock input accepting differential AC-coupled (10-200MHz), single-ended LVCMOS (10-200MHz), or crystal oscillator (10-50MHz) with internal bias in differential mode. |+| 2 | SECREF_N | input | Secondary external clock input paired with SECREF_P (serves as crystal XIN), requires AC coupling capacitor in differential mode with internal bias disabled in single-ended or crystal modes. |+| 3 | VDD_REF | power_in | Power supply for reference input block and digital core, 1.8V/2.5V/3.3V ±5%. |+| 4 | REFSEL | input | Reference input selection pin (tri-state) with 50kΩ weak pull-up/pull-down, selects primary or secondary reference input. |+| 5 | PRIREF_P | input | Primary reference clock input accepting differential AC-coupled (10-200MHz) or single-ended LVCMOS (10-200MHz) with internal bias in differential mode. |+| 6 | PRIREF_N | input | Primary reference clock input paired with PRIREF_P, requires AC coupling in differential mode with internal bias disabled in single-ended mode. |+| 7 | OUT0 | output | LVCMOS output supporting frequencies 24kHz to 200MHz with configurable slew rate and reference input bypass capability. |+| 8 | PDN | input | Power-down/reset input (active low) or SYNCN, with 50kΩ weak pull-up resistor (disabled when configured as output). |+| 9 | OUT4_N | output | Differential output pair 4 negative side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |+| 10 | OUT4_P | output | Differential output pair 4 positive side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |+| 11 | GPIO4 | bidirectional | General-purpose input/output capable of status output or GPIO input operation with programmable behavior. |+| 12 | SCL/GPIO3 | input | I2C serial clock (SCL) or GPIO3 input with fail-safe circuitry, requires external pull-up to VDD_REF in I2C mode (400kHz maximum). |+| 13 | OUT3_N | output | Differential output pair 3 negative side supporting LVDS/LP-HCSL-like formats with programmable driver. |+| 14 | OUT3_P | output | Differential output pair 3 positive side supporting LVDS/LP-HCSL-like formats with programmable driver. |+| 15 | VDDO_34 | power_in | Power supply for output channels 0, 3, and 4, accepts 1.8V/2.5V/3.3V ±5% with independent voltage configuration. |+| 16 | VDDO_12 | power_in | Power supply for output channels 1 and 2, accepts 1.8V/2.5V/3.3V ±5% with independent voltage configuration. |+| 17 | OUT2_N | output | Differential output pair 2 negative side supporting LVDS/LP-HCSL-like formats with programmable driver. |+| 18 | OUT2_P | output | Differential output pair 2 positive side supporting LVDS/LP-HCSL-like formats with programmable driver. |+| 19 | SDA/GPIO2 | bidirectional | I2C serial data (SDA) input/output (open-drain, bidirectional) or GPIO2 input with fail-safe circuitry, requires external pull-up to VDD_REF in I2C mode. |+| 20 | GPIO1 | bidirectional | General-purpose input/output capable of status output or GPIO input operation with programmable behavior. |+| 21 | OUT1_N | output | Differential output pair 1 negative side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |+| 22 | OUT1_P | output | Differential output pair 1 positive side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |+| 23 | HW_SW_CTRL | input | EEPROM page selection pin (tri-state) with 50kΩ weak pull-up/pull-down, selects EEPROM page 0/1 or enables I2C fallback mode when floating. |+| 24 | VDD_VCO | power_in | Power supply for PLL and VCO, accepts 1.8V/2.5V/3.3V ±5% with internal LDO regulation. |+| 25 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24(4x4) |+| Category | Clock/Timing |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `CDCE6214RGET`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`+- 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)+- 3D model files: `cdce6214rget-etched.step` / `cdce6214rget-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdce6214rget.step` / `cdce6214rget.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdce6214) (59 pp, sha256 `63c69e102ec6bdb6`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdce6214rget-datasheet.pdf)
page.jsonadded+302@@ -0,0 +1,302 @@+{+ "slug": "cdce6214rget",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdce6214rget",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdce6214rget.kicad_sym",+ "cdce6214rget.kicad_mod",+ "cdce6214rget.glb",+ "cdce6214rget.step",+ "cdce6214rget.lbr",+ "docs/hero.png",+ "docs/cdce6214rget-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cdce6214rget-hero.glb",+ "cdce6214rget-hero.overlay.json"+ ],+ "component": {+ "mpn": "CDCE6214RGET",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24(4x4)",+ "pin_count": 25,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cdce6214",+ "parts": {+ "symbol": "cdce6214rget.kicad_sym",+ "footprint": "cdce6214rget.kicad_mod",+ "model_3d": "cdce6214rget-hero.glb",+ "model_3d_plain": "cdce6214rget.glb",+ "model_3d_step": "cdce6214rget-etched.step",+ "model_3d_step_plain": "cdce6214rget.step",+ "lbr": "cdce6214rget.lbr"+ },+ "distributor_links": {+ "lcsc": "C2864591",+ "digikey": "296-CDCE6214RGETTR-ND",+ "mouser": "595-CDCE6214RGET"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T01:32:46Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-CDCE6214RGETTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-CDCE6214RGET",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SECREF_P",+ "type": "input",+ "description": "Secondary external clock input accepting differential AC-coupled (10-200MHz), single-ended LVCMOS (10-200MHz), or crystal oscillator (10-50MHz) with internal bias in differential mode."+ },+ {+ "number": "2",+ "name": "SECREF_N",+ "type": "input",+ "description": "Secondary external clock input paired with SECREF_P (serves as crystal XIN), requires AC coupling capacitor in differential mode with internal bias disabled in single-ended or crystal modes."+ },+ {+ "number": "3",+ "name": "VDD_REF",+ "type": "power_in",+ "description": "Power supply for reference input block and digital core, 1.8V/2.5V/3.3V ±5%."+ },+ {+ "number": "4",+ "name": "REFSEL",+ "type": "input",+ "description": "Reference input selection pin (tri-state) with 50kΩ weak pull-up/pull-down, selects primary or secondary reference input."+ },+ {+ "number": "5",+ "name": "PRIREF_P",+ "type": "input",+ "description": "Primary reference clock input accepting differential AC-coupled (10-200MHz) or single-ended LVCMOS (10-200MHz) with internal bias in differential mode."+ },+ {+ "number": "6",+ "name": "PRIREF_N",+ "type": "input",+ "description": "Primary reference clock input paired with PRIREF_P, requires AC coupling in differential mode with internal bias disabled in single-ended mode."+ },+ {+ "number": "7",+ "name": "OUT0",+ "type": "output",+ "description": "LVCMOS output supporting frequencies 24kHz to 200MHz with configurable slew rate and reference input bypass capability."+ },+ {+ "number": "8",+ "name": "PDN",+ "type": "input",+ "description": "Power-down/reset input (active low) or SYNCN, with 50kΩ weak pull-up resistor (disabled when configured as output)."+ },+ {+ "number": "9",+ "name": "OUT4_N",+ "type": "output",+ "description": "Differential output pair 4 negative side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver."+ },+ {+ "number": "10",+ "name": "OUT4_P",+ "type": "output",+ "description": "Differential output pair 4 positive side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver."+ },+ {+ "number": "11",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose input/output capable of status output or GPIO input operation with programmable behavior."+ },+ {+ "number": "12",+ "name": "SCL/GPIO3",+ "type": "input",+ "description": "I2C serial clock (SCL) or GPIO3 input with fail-safe circuitry, requires external pull-up to VDD_REF in I2C mode (400kHz maximum)."+ },+ {+ "number": "13",+ "name": "OUT3_N",+ "type": "output",+ "description": "Differential output pair 3 negative side supporting LVDS/LP-HCSL-like formats with programmable driver."+ },+ {+ "number": "14",+ "name": "OUT3_P",+ "type": "output",+ "description": "Differential output pair 3 positive side supporting LVDS/LP-HCSL-like formats with programmable driver."+ },+ {+ "number": "15",+ "name": "VDDO_34",+ "type": "power_in",+ "description": "Power supply for output channels 0, 3, and 4, accepts 1.8V/2.5V/3.3V ±5% with independent voltage configuration."+ },+ {+ "number": "16",+ "name": "VDDO_12",+ "type": "power_in",+ "description": "Power supply for output channels 1 and 2, accepts 1.8V/2.5V/3.3V ±5% with independent voltage configuration."+ },+ {+ "number": "17",+ "name": "OUT2_N",+ "type": "output",+ "description": "Differential output pair 2 negative side supporting LVDS/LP-HCSL-like formats with programmable driver."+ },+ {+ "number": "18",+ "name": "OUT2_P",+ "type": "output",+ "description": "Differential output pair 2 positive side supporting LVDS/LP-HCSL-like formats with programmable driver."+ },+ {+ "number": "19",+ "name": "SDA/GPIO2",+ "type": "bidirectional",+ "description": "I2C serial data (SDA) input/output (open-drain, bidirectional) or GPIO2 input with fail-safe circuitry, requires external pull-up to VDD_REF in I2C mode."+ },+ {+ "number": "20",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose input/output capable of status output or GPIO input operation with programmable behavior."+ },+ {+ "number": "21",+ "name": "OUT1_N",+ "type": "output",+ "description": "Differential output pair 1 negative side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver."+ },+ {+ "number": "22",+ "name": "OUT1_P",+ "type": "output",+ "description": "Differential output pair 1 positive side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver."+ },+ {+ "number": "23",+ "name": "HW_SW_CTRL",+ "type": "input",+ "description": "EEPROM page selection pin (tri-state) with 50kΩ weak pull-up/pull-down, selects EEPROM page 0/1 or enables I2C fallback mode when floating."+ },+ {+ "number": "24",+ "name": "VDD_VCO",+ "type": "power_in",+ "description": "Power supply for PLL and VCO, accepts 1.8V/2.5V/3.3V ±5% with internal LDO regulation."+ },+ {+ "number": "25",+ "name": "DAP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 25 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 44,+ "cost_usd": 0.3978,+ "at": "2026-10-07T01:32:30"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cdce6214",+ "pages": 59,+ "sha256": "63c69e102ec6bdb6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cdce6214rget.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cdce6214rget-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 4,+ 4,+ 0.77+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b52d713b3437b34b5f035864e828de20998d4f9d2fe288bb7bf1e35602e657a7",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}