component
CDCE6214RGET
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCDCE6214RGET
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-24(4x4)
CDCE6214RGET from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SECREF_P | input | Secondary external clock input accepting differential AC-coupled (10-200MHz), single-ended LVCMOS (10-200MHz), or crystal oscillator (10-50MHz) with internal bias in differential mode. |
| 2 | SECREF_N | input | Secondary external clock input paired with SECREF_P (serves as crystal XIN), requires AC coupling capacitor in differential mode with internal bias disabled in single-ended or crystal modes. |
| 3 | VDD_REF | power_in | Power supply for reference input block and digital core, 1.8V/2.5V/3.3V ±5%. |
| 4 | REFSEL | input | Reference input selection pin (tri-state) with 50kΩ weak pull-up/pull-down, selects primary or secondary reference input. |
| 5 | PRIREF_P | input | Primary reference clock input accepting differential AC-coupled (10-200MHz) or single-ended LVCMOS (10-200MHz) with internal bias in differential mode. |
| 6 | PRIREF_N | input | Primary reference clock input paired with PRIREF_P, requires AC coupling in differential mode with internal bias disabled in single-ended mode. |
| 7 | OUT0 | output | LVCMOS output supporting frequencies 24kHz to 200MHz with configurable slew rate and reference input bypass capability. |
| 8 | PDN | input | Power-down/reset input (active low) or SYNCN, with 50kΩ weak pull-up resistor (disabled when configured as output). |
| 9 | OUT4_N | output | Differential output pair 4 negative side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |
| 10 | OUT4_P | output | Differential output pair 4 positive side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |
| 11 | GPIO4 | bidirectional | General-purpose input/output capable of status output or GPIO input operation with programmable behavior. |
| 12 | SCL/GPIO3 | input | I2C serial clock (SCL) or GPIO3 input with fail-safe circuitry, requires external pull-up to VDD_REF in I2C mode (400kHz maximum). |
| 13 | OUT3_N | output | Differential output pair 3 negative side supporting LVDS/LP-HCSL-like formats with programmable driver. |
| 14 | OUT3_P | output | Differential output pair 3 positive side supporting LVDS/LP-HCSL-like formats with programmable driver. |
| 15 | VDDO_34 | power_in | Power supply for output channels 0, 3, and 4, accepts 1.8V/2.5V/3.3V ±5% with independent voltage configuration. |
| 16 | VDDO_12 | power_in | Power supply for output channels 1 and 2, accepts 1.8V/2.5V/3.3V ±5% with independent voltage configuration. |
| 17 | OUT2_N | output | Differential output pair 2 negative side supporting LVDS/LP-HCSL-like formats with programmable driver. |
| 18 | OUT2_P | output | Differential output pair 2 positive side supporting LVDS/LP-HCSL-like formats with programmable driver. |
| 19 | SDA/GPIO2 | bidirectional | I2C serial data (SDA) input/output (open-drain, bidirectional) or GPIO2 input with fail-safe circuitry, requires external pull-up to VDD_REF in I2C mode. |
| 20 | GPIO1 | bidirectional | General-purpose input/output capable of status output or GPIO input operation with programmable behavior. |
| 21 | OUT1_N | output | Differential output pair 1 negative side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |
| 22 | OUT1_P | output | Differential output pair 1 positive side supporting LVDS/LP-HCSL-like or LVCMOS formats with programmable driver. |
| 23 | HW_SW_CTRL | input | EEPROM page selection pin (tri-state) with 50kΩ weak pull-up/pull-down, selects EEPROM page 0/1 or enables I2C fallback mode when floating. |
| 24 | VDD_VCO | power_in | Power supply for PLL and VCO, accepts 1.8V/2.5V/3.3V ±5% with internal LDO regulation. |
| 25 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Clock/Timing |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
CDCE6214RGET - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
cdce6214rget-etched.step/cdce6214rget-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdce6214rget.step/cdce6214rget.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (59 pp, sha256
63c69e102ec6bdb6, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).