component
CDCE6214RGER
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+62@@ -0,0 +1,62 @@+# CDCE6214RGER++**Texas Instruments** · Clock Generators, PLLs, Frequency Synthesizers · VQFN-24(4x4)++CDCE6214RGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SECREF_P | input | Secondary reference clock input accepting differential, single-ended, or crystal input with AC coupling capacitor required for differential mode and internal bias disabled in single-ended and crystal modes. |+| 2 | SECREF_N | input | Secondary reference clock differential pair with SECREF_P, serving as XIN for crystal connection and requiring AC coupling capacitor in differential mode with internal bias. |+| 3 | VDD_REF | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for reference input buffer and digital control circuitry. |+| 4 | REFSEL | input | Manual selection pin (three-state) for reference input multiplexer with weak pull-up and pull-down resistors (RPU = RPD = 50kΩ). |+| 5 | PRIREF_P | input | Primary reference clock input accepting differential or single-ended input with AC coupling capacitor required for differential mode and internal bias disabled in single-ended mode. |+| 6 | PRIREF_N | input | Primary reference clock differential pair with PRIREF_P requiring AC coupling capacitor in differential mode with internal bias. |+| 7 | OUT0 | output | LVCMOS output with configurable slew rate capable of bypassing reference input clock directly to output. |+| 8 | PDN | input | Power down/reset input (active low) or SYNCN with weak pull-up resistor (RPU = 50kΩ) disabled in output mode. |+| 9 | OUT4_N | output | Differential pair output 4 negative supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |+| 10 | OUT4_P | output | Differential pair output 4 positive supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |+| 11 | GPIO4 | bidirectional | General-purpose input/output configured as status output or GPIO4 input for system control. |+| 12 | SCL/GPIO3 | input | I2C serial clock or GPIO3 input requiring external pull-up resistor to VDD_REF in I2C mode with fail-safe input. |+| 13 | OUT3_N | output | Differential pair output 3 negative supporting LVDS-like or LP-HCSL output format with programmable driver. |+| 14 | OUT3_P | output | Differential pair output 3 positive supporting LVDS-like or LP-HCSL output format with programmable driver. |+| 15 | VDDO_34 | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for OUT0, OUT3, and OUT4 output channels and drivers. |+| 16 | VDDO_12 | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for OUT1 and OUT2 differential output channels. |+| 17 | OUT2_N | output | Differential pair output 2 negative supporting LVDS-like or LP-HCSL output format with programmable driver. |+| 18 | OUT2_P | output | Differential pair output 2 positive supporting LVDS-like or LP-HCSL output format with programmable driver. |+| 19 | SDA/GPIO2 | bidirectional | I2C serial data (open-drain, bidirectional) or GPIO2 input requiring external pull-up resistor to VDD_REF in I2C mode with fail-safe input. |+| 20 | GPIO1 | bidirectional | General-purpose input/output configured as status output or GPIO1 input for system control. |+| 21 | OUT1_N | output | Differential pair output 1 negative supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |+| 22 | OUT1_P | output | Differential pair output 1 positive supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |+| 23 | HW_SW_CTRL | input | Manual selection pin (three-state) for EEPROM page selection with weak pull-up and pull-down resistors (RPU = RPD = 50kΩ). |+| 24 | VDD_VCO | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for PLL, VCO, and charge pump circuitry. |+| 25 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-24(4x4) |+| Category | Clock/Timing |+| Pins | 25 |++## CAD (KiCad official)++- Symbol: `CDCE6214RGER`+- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`+- 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)+- 3D model files: `cdce6214rger-etched.step` / `cdce6214rger-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cdce6214rger.step` / `cdce6214rger.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cdce6214) (59 pp, sha256 `63c69e102ec6bdb6`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cdce6214rger-datasheet.pdf)
page.jsonadded+260@@ -0,0 +1,260 @@+{+ "slug": "cdce6214rger",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "clock-timing",+ "cdce6214rger",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cdce6214rger.kicad_sym",+ "cdce6214rger.kicad_mod",+ "cdce6214rger.glb",+ "cdce6214rger.step",+ "cdce6214rger.lbr",+ "docs/hero.png",+ "docs/cdce6214rger-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CDCE6214RGER",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-24(4x4)",+ "pin_count": 25,+ "category": "Clock/Timing",+ "subcategory": "Clock Generators, PLLs, Frequency Synthesizers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cdce6214",+ "parts": {+ "symbol": "cdce6214rger.kicad_sym",+ "footprint": "cdce6214rger.kicad_mod",+ "model_3d": "cdce6214rger-etched.glb",+ "model_3d_plain": "cdce6214rger.glb",+ "model_3d_step": "cdce6214rger-etched.step",+ "model_3d_step_plain": "cdce6214rger.step",+ "lbr": "cdce6214rger.lbr"+ },+ "distributor_links": {+ "lcsc": "C3608351",+ "digikey": "296-CDCE6214RGERTR-ND",+ "mouser": "595-CDCE6214RGER"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T09:14:45Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-CDCE6214RGERTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-CDCE6214RGER",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SECREF_P",+ "type": "input",+ "description": "Secondary reference clock input accepting differential, single-ended, or crystal input with AC coupling capacitor required for differential mode and internal bias disabled in single-ended and crystal modes."+ },+ {+ "number": "2",+ "name": "SECREF_N",+ "type": "input",+ "description": "Secondary reference clock differential pair with SECREF_P, serving as XIN for crystal connection and requiring AC coupling capacitor in differential mode with internal bias."+ },+ {+ "number": "3",+ "name": "VDD_REF",+ "type": "power_in",+ "description": "1.8V, 2.5V, or 3.3V (±5%) power supply for reference input buffer and digital control circuitry."+ },+ {+ "number": "4",+ "name": "REFSEL",+ "type": "input",+ "description": "Manual selection pin (three-state) for reference input multiplexer with weak pull-up and pull-down resistors (RPU = RPD = 50kΩ)."+ },+ {+ "number": "5",+ "name": "PRIREF_P",+ "type": "input",+ "description": "Primary reference clock input accepting differential or single-ended input with AC coupling capacitor required for differential mode and internal bias disabled in single-ended mode."+ },+ {+ "number": "6",+ "name": "PRIREF_N",+ "type": "input",+ "description": "Primary reference clock differential pair with PRIREF_P requiring AC coupling capacitor in differential mode with internal bias."+ },+ {+ "number": "7",+ "name": "OUT0",+ "type": "output",+ "description": "LVCMOS output with configurable slew rate capable of bypassing reference input clock directly to output."+ },+ {+ "number": "8",+ "name": "PDN",+ "type": "input",+ "description": "Power down/reset input (active low) or SYNCN with weak pull-up resistor (RPU = 50kΩ) disabled in output mode."+ },+ {+ "number": "9",+ "name": "OUT4_N",+ "type": "output",+ "description": "Differential pair output 4 negative supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver."+ },+ {+ "number": "10",+ "name": "OUT4_P",+ "type": "output",+ "description": "Differential pair output 4 positive supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver."+ },+ {+ "number": "11",+ "name": "GPIO4",+ "type": "bidirectional",+ "description": "General-purpose input/output configured as status output or GPIO4 input for system control."+ },+ {+ "number": "12",+ "name": "SCL/GPIO3",+ "type": "input",+ "description": "I2C serial clock or GPIO3 input requiring external pull-up resistor to VDD_REF in I2C mode with fail-safe input."+ },+ {+ "number": "13",+ "name": "OUT3_N",+ "type": "output",+ "description": "Differential pair output 3 negative supporting LVDS-like or LP-HCSL output format with programmable driver."+ },+ {+ "number": "14",+ "name": "OUT3_P",+ "type": "output",+ "description": "Differential pair output 3 positive supporting LVDS-like or LP-HCSL output format with programmable driver."+ },+ {+ "number": "15",+ "name": "VDDO_34",+ "type": "power_in",+ "description": "1.8V, 2.5V, or 3.3V (±5%) power supply for OUT0, OUT3, and OUT4 output channels and drivers."+ },+ {+ "number": "16",+ "name": "VDDO_12",+ "type": "power_in",+ "description": "1.8V, 2.5V, or 3.3V (±5%) power supply for OUT1 and OUT2 differential output channels."+ },+ {+ "number": "17",+ "name": "OUT2_N",+ "type": "output",+ "description": "Differential pair output 2 negative supporting LVDS-like or LP-HCSL output format with programmable driver."+ },+ {+ "number": "18",+ "name": "OUT2_P",+ "type": "output",+ "description": "Differential pair output 2 positive supporting LVDS-like or LP-HCSL output format with programmable driver."+ },+ {+ "number": "19",+ "name": "SDA/GPIO2",+ "type": "bidirectional",+ "description": "I2C serial data (open-drain, bidirectional) or GPIO2 input requiring external pull-up resistor to VDD_REF in I2C mode with fail-safe input."+ },+ {+ "number": "20",+ "name": "GPIO1",+ "type": "bidirectional",+ "description": "General-purpose input/output configured as status output or GPIO1 input for system control."+ },+ {+ "number": "21",+ "name": "OUT1_N",+ "type": "output",+ "description": "Differential pair output 1 negative supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver."+ },+ {+ "number": "22",+ "name": "OUT1_P",+ "type": "output",+ "description": "Differential pair output 1 positive supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver."+ },+ {+ "number": "23",+ "name": "HW_SW_CTRL",+ "type": "input",+ "description": "Manual selection pin (three-state) for EEPROM page selection with weak pull-up and pull-down resistors (RPU = RPD = 50kΩ)."+ },+ {+ "number": "24",+ "name": "VDD_VCO",+ "type": "power_in",+ "description": "1.8V, 2.5V, or 3.3V (±5%) power supply for PLL, VCO, and charge pump circuitry."+ },+ {+ "number": "25",+ "name": "DAP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 25 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 44,+ "cost_usd": 0.367,+ "at": "2026-10-01T09:14:27"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cdce6214",+ "pages": 59,+ "sha256": "63c69e102ec6bdb6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 25,+ "described": 25,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}