component
CDCE6214RGER
Public Made by Adomby adom
Texas Instruments Clock Generators, PLLs, Frequency Synthesizers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCDCE6214RGER
Texas Instruments · Clock Generators, PLLs, Frequency Synthesizers · VQFN-24(4x4)
CDCE6214RGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SECREF_P | input | Secondary reference clock input accepting differential, single-ended, or crystal input with AC coupling capacitor required for differential mode and internal bias disabled in single-ended and crystal modes. |
| 2 | SECREF_N | input | Secondary reference clock differential pair with SECREF_P, serving as XIN for crystal connection and requiring AC coupling capacitor in differential mode with internal bias. |
| 3 | VDD_REF | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for reference input buffer and digital control circuitry. |
| 4 | REFSEL | input | Manual selection pin (three-state) for reference input multiplexer with weak pull-up and pull-down resistors (RPU = RPD = 50kΩ). |
| 5 | PRIREF_P | input | Primary reference clock input accepting differential or single-ended input with AC coupling capacitor required for differential mode and internal bias disabled in single-ended mode. |
| 6 | PRIREF_N | input | Primary reference clock differential pair with PRIREF_P requiring AC coupling capacitor in differential mode with internal bias. |
| 7 | OUT0 | output | LVCMOS output with configurable slew rate capable of bypassing reference input clock directly to output. |
| 8 | PDN | input | Power down/reset input (active low) or SYNCN with weak pull-up resistor (RPU = 50kΩ) disabled in output mode. |
| 9 | OUT4_N | output | Differential pair output 4 negative supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |
| 10 | OUT4_P | output | Differential pair output 4 positive supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |
| 11 | GPIO4 | bidirectional | General-purpose input/output configured as status output or GPIO4 input for system control. |
| 12 | SCL/GPIO3 | input | I2C serial clock or GPIO3 input requiring external pull-up resistor to VDD_REF in I2C mode with fail-safe input. |
| 13 | OUT3_N | output | Differential pair output 3 negative supporting LVDS-like or LP-HCSL output format with programmable driver. |
| 14 | OUT3_P | output | Differential pair output 3 positive supporting LVDS-like or LP-HCSL output format with programmable driver. |
| 15 | VDDO_34 | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for OUT0, OUT3, and OUT4 output channels and drivers. |
| 16 | VDDO_12 | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for OUT1 and OUT2 differential output channels. |
| 17 | OUT2_N | output | Differential pair output 2 negative supporting LVDS-like or LP-HCSL output format with programmable driver. |
| 18 | OUT2_P | output | Differential pair output 2 positive supporting LVDS-like or LP-HCSL output format with programmable driver. |
| 19 | SDA/GPIO2 | bidirectional | I2C serial data (open-drain, bidirectional) or GPIO2 input requiring external pull-up resistor to VDD_REF in I2C mode with fail-safe input. |
| 20 | GPIO1 | bidirectional | General-purpose input/output configured as status output or GPIO1 input for system control. |
| 21 | OUT1_N | output | Differential pair output 1 negative supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |
| 22 | OUT1_P | output | Differential pair output 1 positive supporting LVDS-like, LP-HCSL, or LVCMOS output format with programmable driver. |
| 23 | HW_SW_CTRL | input | Manual selection pin (three-state) for EEPROM page selection with weak pull-up and pull-down resistors (RPU = RPD = 50kΩ). |
| 24 | VDD_VCO | power_in | 1.8V, 2.5V, or 3.3V (±5%) power supply for PLL, VCO, and charge pump circuitry. |
| 25 | DAP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24(4x4) |
| Category | Clock/Timing |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
CDCE6214RGER - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
- 3D model files:
cdce6214rger-etched.step/cdce6214rger-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cdce6214rger.step/cdce6214rger.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (59 pp, sha256
63c69e102ec6bdb6, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).